WARNING:Xst:1710: Help me with verilog and ISE

I am trying to make a simple FIFO buffer using verilog and ISE 10.1. I keep getting this warning for each bit of "_data_out" and the "_data_out" in RTL schematic is grounded.


WARNING:Xst:1710 - FF/Latch <_data_out_1> (without init value) has a constant value of 0 in block <in_north_0>. This FF/Latch will be trimmed during the optimization process.

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////////////////
module buffer(
input _clk, // clock
input _rst, // reset
input wire [63:0] _data_in, // input data
input _w_en, // write_enable
input _r_en, // read enable
output reg [63:0] _data_out, // output data
output reg _full, // if 0 buffer is full
);
parameter data_width=64;

reg [data_width-1:0] mem0; reg [data_width-1:0] mem1;
reg [data_width-1:0] mem2; reg [data_width-1:0] mem3;
reg [data_width-1:0] mem4; reg [data_width-1:0] mem5;
reg [data_width-1:0] mem6; reg [data_width-1:0] mem7;

// _full is empty0;
reg empty1; reg empty2; reg empty3; reg empty4;
reg empty5; reg empty6; reg empty7;

always @(posedge _clk)
begin
/////////////////////////////////Reset//////////////////////////////////
if (_rst==1)
begin
mem0=0; mem1=0; mem2=0; mem3=0;
mem4=0; mem5=0; mem6=0; mem7=0;
_full=1; empty1=1; empty2=1; empty3=1;
empty4=1; empty5=1; empty6=1; empty7=1;
_port_id=0; _port_r=0;
end
else
begin

////////////////////////////Read///////////////////////////////////////
if (_r_en==1) begin
_data_out=mem7;
mem7=0;
empty7=1; end
///////////////////////////////////////////////////////////////////////

if (empty7==1) begin
if (mem6!=0) begin
mem7=mem6;
empty7=0;
mem6=0;
empty6=1; end end

if (empty6==1) begin
if (mem5!=0) begin
mem6=mem5;
empty6=0;
mem5=0;
empty5=1; end end

if (empty5==1) begin
if (mem4!=0) begin
mem5=mem4;
empty5=0;
mem4=0;
empty4=1; end end

if (empty4==1) begin
if (mem3!=0) begin
mem4=mem3;
empty4=0;
mem3=0;
empty3=1; end end

if (empty3==1) begin
if (mem2!=0) begin
mem3=mem2;
empty3=0;
mem2=0;
empty2=1; end end

if (empty2==1) begin
if (mem1!=0) begin
mem2=mem1;
empty2=0;
mem1=0;
empty1=1; end end

if (empty1==1) begin
if (mem0!=0) begin
mem1=mem0;
empty1=0;
_full=1; end end

///////////////////////////Write//////////////////////////////////////
if (_full==1 && _w_en==1) begin
mem0=_data_in;
_full=0; end
///////////////////////////////////////////////////////////////////////

end //else

end
endmodule

Synthesizer optimizes your codes and thinks that you have never changed the value of 1.bit of data_out. So that it gives you a warning that it will be trimmed(it isn't used) in real hardware)..
Everytime, check for warnings.. It's more challenging than errors.. and gives you more view about your codes..

Good luck...