raghava
Member level 2
HI all,
I am in the process of conversting some verilog code snippet to VHDL.
WHat might be the equivalent VHDL code for the following verilog code.
This code is part of my verilog header file.
Expecting answers.
************************8
`define SHAPES 1
`ifdef SHAPES
parameter INPUT_BMP = "../data/input/shapes.bmp";
parameter WL = 8;
parameter IR = 13'd384;
parameter IC = 13'd512;
parameter THRESHOLD = 200;
parameter OUTPUT_BMP = "../data/output/corner_shapes.bmp";
`endif
Added after 1 hours 33 minutes:
HI all,
The equivalent for 'ifdef is in VHDL is
if <boolean expression> generate
<conditional compiled code>
end generate;
But my issue is where it should be placed in the code.
I am expecting answers.
I am in the process of conversting some verilog code snippet to VHDL.
WHat might be the equivalent VHDL code for the following verilog code.
This code is part of my verilog header file.
Expecting answers.
************************8
`define SHAPES 1
`ifdef SHAPES
parameter INPUT_BMP = "../data/input/shapes.bmp";
parameter WL = 8;
parameter IR = 13'd384;
parameter IC = 13'd512;
parameter THRESHOLD = 200;
parameter OUTPUT_BMP = "../data/output/corner_shapes.bmp";
`endif
Added after 1 hours 33 minutes:
HI all,
The equivalent for 'ifdef is in VHDL is
if <boolean expression> generate
<conditional compiled code>
end generate;
But my issue is where it should be placed in the code.
I am expecting answers.