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What is VHDL equivalent for this verilog code

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raghava

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HI all,

I am in the process of conversting some verilog code snippet to VHDL.
WHat might be the equivalent VHDL code for the following verilog code.
This code is part of my verilog header file.

Expecting answers.

************************8

`define SHAPES 1


`ifdef SHAPES
parameter INPUT_BMP = "../data/input/shapes.bmp";
parameter WL = 8;
parameter IR = 13'd384;
parameter IC = 13'd512;
parameter THRESHOLD = 200;
parameter OUTPUT_BMP = "../data/output/corner_shapes.bmp";
`endif

Added after 1 hours 33 minutes:

HI all,

The equivalent for 'ifdef is in VHDL is

if <boolean expression> generate
<conditional compiled code>
end generate;

But my issue is where it should be placed in the code.

I am expecting answers.
 

VHDL has no similar method to supply conditional parameters as with a Verilog 'ifdef. The best solution depends on the
respective purpose. Promising candidates are:

- constant arrays and a generic constant as index

- define all conditional parameters in a package and change the package to get a different variant

Generally, I suggest to consult a verbose VHDL text book or reference manual to learn about the VHDL language concepts. The
Synopsys manual is profound.
 

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    raghava

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