Dynamic power dissipation - combinational vs sequential

How can we distinguish between dynamic power dissipation in a combinational circuit vs power dissipation in a sequential circuit (If both use the same number of transistors - the functionality of both the circuits may differ).........Both are made up of CMOS.......Clock are fed to sequential circuit and register outputs are fed to combinational circuit. Clock toggles each cycle, assume that the inputs to combinational circuit also toggle each cycle

ie Toggle rate of combinational logic inputs = toggle rate of clock (frequency same)

How can we infer about the dynamic power dissipation? Just because of the clock factor can we say that power dissipation is more in sequential circuits........

The dynamic power dissipation is actually data dependent rite??? Please help me