text File reading and writing in VHDL

HI all,
This is the testbench on which I am working. It consists of text (Image pixel data) file reading and writing. I am facing problem in doing so. Can anybody could correct my test bench where file reading and writing is taking place.
I am newbie to VHDL and I am facing problem here. Please help me in this regard.


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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
use STD.textio.all;

ENTITY testbench IS
END testbench;

ARCHITECTURE behavior OF testbench IS

--parameter declaration;
constant WL : integer:= 8;
constant IR : integer:= 64;
constant IC : integer:= 64;
constant THRESHOLD : integer:= 2000;
constant K_SIZE : integer:= 3;

-- Component Declaration for the Unit Under Test (UUT)


-- Clock period definitions
constant i_clk_period : time := 1us;

-- internal signal declaration....
type memory_0 is array (0 to IR*IC-1) of integer;
type memory_1 is array (0 to 8) of integer;
type memory_2 is array (0 to 8) of real;
type memory_3 is array (0 to IR*IC-1) of real;
type memory_4 is array (0 to 53) of std_logic_vector (7 downto 0);

signal pixelImage, thresh, RTL_output : memory_0;
signal dx, dy : memory_1;
signal gaussian, kernel, non : memory_2;
signal p, conv_in, ix, iy, ix2, iy2, ixiy : memory_3;
signal A_matrix, B_matrix, C_matrix, cornerness, non_max, conv_out : memory_3;
signal header_data : memory_4;
signal start_count: std_logic;
signal done: std_logic;



procedure PrepareInput is
VARIABLE inLine : LINE;
VARIABLE dataRead : REAL;
VARIABLE index : integer:= 0;

file file_in : text open read_mode is "../data/input/lena_64_64.txt";
begin

while(not ENDFILE(file_in)) loop
READLINE(file_in, inLine);
exit when endfile (file_in);
READ(inLine, dataRead);
-- pixelImage(index+1) <=integer'value(s);
pixelImage(index+1) <= integer(dataRead);
end loop;

file_close(file_in);

end PrepareInput;

procedure load_rc is
begin
start_count <= '1';
if(i_clk'event and i_clk = '0') then
i_R <= std_logic_vector(to_unsigned(IR, 13));
i_C <= std_logic_vector(to_unsigned(IC, 13));
end if;
end load_rc;

--..........sending data to RTL core
procedure PrepareInput_RTL is
variable a, b: integer;
begin
load_rc;
report"LoadRC is done\n";

for a in 0 to IR loop
for b in 0 to IC loop
if(i_clk'event and i_clk = '0') then
i_pixel_data <= std_logic_vector(to_unsigned(integer(pixelImage(a*IC+b)), 8));
i_data_valid <= '1';
if(a = 0 and b = 0) then
i_start_image <= '1';
i_end_image <= '0';
elsif(a = IR-1 and b =IC-1) then
i_end_image <= '1';
i_start_image <= '0';
else
i_start_image <= '0';
i_end_image <= '0';
end if;

if(a = IR and b = IC) then
i_end_image <= '0';
i_data_valid <= '0';
end if;
end if;
end loop;
if(a = IR-1 and b = IC) then
if(i_clk'event and i_clk = '0') then
i_end_image <= '0';
i_data_valid <= '0';
end if;
end if;

if(a< IR-1) then
if(i_clk'event and i_clk = '0') then
i_data_valid <= '0';
end if;
if(i_clk'event and i_clk = '0') then
i_data_valid <= '0';
end if;
end if;
end loop;
end PrepareInput_RTL;

procedure convolution_task is
variable d, rowTotal, colTotal, center, conv_address : integer;
begin
center := 1;
conv_address := 0;
for row in 0 to IR loop
for col in 0 to IC loop
d := 0;
for rowOffset in -center to center loop
for colOffset in -center to center loop
rowTotal := row + rowOffset;
colTotal := col+colOffset;
if(rowTotal < 0 or rowTotal > IR-1 or colTotal < 0 or colTotal > IC-1) then
p(d) <= real(0);
else
p(d) <= conv_in(rowTotal*IC+colTotal);
end if;
d := d+1;
end loop;
end loop;

conv_out(conv_address) <= p(0) * kernel(8) + p(1) * kernel(7) + p(2) * kernel(6) +
p(3) * kernel(5) + p(4) * kernel(4) + p(5) * kernel(3) +
p(6) * kernel(2) + p(7) * kernel(1) + p(8) * kernel(0) ;

conv_address := conv_address +1;
end loop;
end loop;
end convolution_task;



procedure find_mult is
begin
for i in 0 to IR loop
for j in 0 to IC loop
ix2(i*IC+j) <= ix(i*IC+j) * ix(i*IC+j);
iy2(i*IC+j) <= iy(i*IC+j) * iy(i*IC+j);
ixiy(i*IC+j) <= ix(i*IC+j) * iy(i*IC+j);
end loop;
end loop;
end find_mult;


procedure find_cornernessmap is
variable corn: real;
begin
for i in 0 to IR loop
for j in 0 to IC loop
corn := ((A_matrix(i*IC+j) * B_matrix(i*IC+j)) - (C_matrix(i*IC+j) * C_matrix(i*IC+j)))- (0.05 * (A_matrix(i*IC+j)+B_matrix(i*IC+j))* (A_matrix(i*IC+j)+B_matrix(i*IC+j)));

cornerness(i*IC+j) <= corn;
end loop;
end loop;
end find_cornernessmap;



procedure non_maximal_sppression is
variable d, rowTotal, colTotal, center: integer;
variable count: integer:=0;
begin
center:= 1;
for row in 0 to IR loop
for col in 0 to IC loop
d := 0;
for rowOffset in -center to center loop
for colOffset in -center to center loop
rowTotal := row+rowOffset;
colTotal := col+colOffset;
if(rowTotal < 0 or rowTotal > IR-1 or colTotal < 0 or colTotal > IC-1) then
non(d) <= real(0);
else
non(d) <= cornerness(rowTotal*IC+colTotal);
end if;
d := d+1;
end loop;
end loop;

count := 0;
for i in 0 to 3 loop
for j in 0 to 3 loop
if(cornerness(row*IC+col) < non(i*3+j)) then
count := 1;
end if;
end loop;
end loop;

if(count = 0) then
non_max(row*IC+col) <= cornerness(row*IC+col);
else
non_max(row*IC+col) <= real(0);
end if;

end loop;
end loop;
end non_maximal_sppression;


procedure Thresholding is
begin
for i in 0 to IR loop
for j in 0 to IC loop
if(non_max(i*IC+j) > real(THRESHOLD)) then
thresh(i*IC+j) <= 255;
else
thresh(i*IC+j) <= 0;
end if;
end loop;
end loop;
end Thresholding;

procedure ready_ix is
begin
for i in 0 to IR loop
for j in 0 to IC loop
conv_in(i*IC+j) <= real(pixelImage(i*IC+j));
end loop;
end loop;

for i in 0 to K_SIZE loop
for j in 0 to K_SIZE loop
kernel(i*K_SIZE+j) <= real(dx(i*K_SIZE+j));
end loop;
end loop;
end ready_ix;

procedure copy_ix is
begin
for i in 0 to IR loop
for j in 0 to IC loop
ix(i*IC+j) <= conv_out(i*IC+j);
end loop;
end loop;
end procedure;

procedure ready_iy is
begin
for i in 0 to K_SIZE loop
for j in 0 to K_SIZE loop
kernel(i*K_SIZE+j) <= real(dy(i*K_SIZE+j));
end loop;
end loop;
end ready_iy;

procedure copy_iy is
begin
for i in 0 to IR loop
for j in 0 to IC loop
iy(i*IC+j) <= conv_out(i*IC+j);
end loop;
end loop;
end copy_iy;

procedure ready_a is
begin
for i in 0 to IR loop
for j in 0 to IC loop
conv_in(i*IC+j) <= ix2(i*IC+j);
end loop;
end loop;

for i in 0 to K_SIZE loop
for j in 0 to K_SIZE loop
kernel(i*K_SIZE+j) <= gaussian(i*K_SIZE+j);
end loop;
end loop;
end ready_a;

procedure copy_a is
begin
for i in 0 to IR loop
for j in 0 to IC loop
A_matrix(i*IC+j) <= conv_out(i*IC+j);
end loop;
end loop;
end copy_a;

procedure ready_b is
begin
for i in 0 to IR loop
for j in 0 to IC loop
conv_in(i*IC+j) <= iy2(i*IC+j);
end loop;
end loop;
end ready_b;

procedure copy_b is
begin
for i in 0 to IR loop
for j in 0 to IC loop
B_matrix(i*IC+j) <= conv_out(i*IC+j);
end loop;
end loop;
end copy_b;

procedure ready_c is
begin
for i in 0 to IR loop
for j in 0 to IC loop
conv_in(i*IC+j) <= iy2(i*IC+j);
end loop;
end loop;
end ready_c;

procedure copy_c is
begin
for i in 0 to IR loop
for j in 0 to IC loop
C_matrix(i*IC+j) <= conv_out(i*IC+j);
end loop;
end loop;
end copy_c;


procedure behavior_HarrisCorner is
begin
ready_ix;
convolution_task;
copy_ix;
report"Ix computation is done\n";

ready_iy;
convolution_task;
copy_iy;
report"Iy computation is done\n";

find_mult;
report"Multiplication of differentiation is done\n";

ready_a;
convolution_task;
copy_a;
report"A computation is done\n";

ready_b;
convolution_task;
copy_b;
report"B computation is done\n";

ready_c;
convolution_task;
copy_c;
report"C_matrix computation is done\n";

find_cornernessmap;
report"Cornerness map is done\n";

non_maximal_sppression;
report"Non-maximum suppression is done\n";

Thresholding;
report"Thresholding is done\n";
end behavior_HarrisCorner;

procedure writeTextData is
variable inline: line;
variable s: string (1 to 10);
file file_out : text open read_mode is "../data/output/RTL_output.txt";
begin
for i in 0 to IR loop
for j in 0 to IC loop
write(inline, RTL_output(i*IC+j));
writeline(file_out, inline);
end loop;
end loop;
end writeTextData;

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: harris_corner_top
generic map(WL=>WL, IR=>IR, IC=>IC, THRESHOLD=>THRESHOLD)
PORT MAP (
i_clk => i_clk,
i_reset => i_reset,
i_R => i_R,
i_C => i_C,
i_start_image => i_start_image,
i_end_image => i_end_image,
i_data_valid => i_data_valid,
i_pixel_data => i_pixel_data,
o_data_valid => o_data_valid,
o_corner_data => o_corner_data,
o_start_image => o_start_image,
o_end_image => o_end_image
);

-- Clock process definitions
i_clk_process rocess
begin
i_clk <= '0';
wait for i_clk_period/2;
i_clk <= '1';
wait for i_clk_period/2;
end process;


-- Stimulus process
stim_proc: process
begin
-- Wait 100 ns for global reset to finish
-- #500;


PrepareInput;
report"PrepareInput is done\n";

behavior_HarrisCorner;
report"behavioral computation of Haris Corner detection is done\n";

PrepareInput_RTL;
report"PrepareInputRTL is done\n";

wait until done = '1';

writeTextData;

assert false report "end of simulation" severity failure;
--wait;
end process;

-- RTL output data capturing.
dataCapture: process(i_clk, i_reset)
variable outAddr: integer:= 0;
begin
if(i_reset = '1') then
outAddr := 0;
done <= '0';
elsif(rising_edge(i_clk)) then
if(o_data_valid = '1') then
RTL_output(outAddr) <= to_integer(unsigned(o_corner_data));
outAddr := outAddr+1;

if(outAddr = IR*IC) then
outAddr :=0;
done <= '1';
end if;
end if;
end if;
end process;

-- number of cycles computatin
-- cycles: process(i_clk, i_reset)
-- variable count_cycle: integer := 0;
-- begin
-- if(i_reset = '1') then
-- count_cycle := 0;
-- elsif(rising_edge(i_clk) then
-- if(done = '1') then
-- --report " Number of cycles taken = %d, count_cycle";
-- else
-- if(start_count = '1') then
-- count_cycle := count_cycle + 1;
-- end if;
-- end if;
-- end if;
-- end process;

END;

Added after 1 minutes:

HI ,

Please run the above testbench by removing the

-- Instantiate the Unit Under Test (UUT)

Expecting your reply.

I have just started learning the VHDL. I found one logical error in the following while loop. Error : The while loop also contain the exit statement which will stop your program evreytime it does the file reading, because the exit statement will be true after the reading the last line in READLINE(....). I am not sure why this exit statement is included in this code.
------------------------------------------------------
while(not ENDFILE(file_in)) loop
READLINE(file_in, inLine);
exit when endfile (file_in);
READ(inLine, dataRead);
-- pixelImage(index+1) <=integer'value(s);
pixelImage(index+1) <= integer(dataRead);
end loop;
------------------------------------------------------

Regards,
Jay

you implemented all the testbench elements here?

What do mean by " you implemented all the testbench elements here??".

HI all,

I am expecting answers form you all.

Hi ,

I am expecting answers