whlinfei
Member level 2
Hi all,
I am using several current mirrors in my design, with 1uA as one unit.
I am not sure about the transistor size that I should use.
Is that any normal standard for the ratio of Vds(eff) over Vth to maintain to keep the biasing stable.
p.s. in the simulation there is no problem, every current mirror in saturation region. but I am gonna fabricate this chip, I am not sure if it will have some problem.
I use 0.13 IBM process.
I am using several current mirrors in my design, with 1uA as one unit.
I am not sure about the transistor size that I should use.
Is that any normal standard for the ratio of Vds(eff) over Vth to maintain to keep the biasing stable.
p.s. in the simulation there is no problem, every current mirror in saturation region. but I am gonna fabricate this chip, I am not sure if it will have some problem.
I use 0.13 IBM process.