Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Time domain & Frequency domain Jitter characterization

Status
Not open for further replies.

AdvaRes

Advanced Member level 4
Joined
Feb 14, 2008
Messages
1,163
Helped
113
Reputation
220
Reaction score
51
Trophy points
1,328
Location
At home
Activity points
7,442
Hi all,

In many papers and tutorials that I read, PLL jitter characterization is done in the time domain or in the frequency domain depending on the application. In the slide 2 and 3 of this tutorial (Michael Perrott) mensioned clearly these applications:
**broken link removed**
For wireless system jitter is characterized in frequency domain (calculated from phase noise), and for high speed serial links (here it includes wired and optical data communication systems) it is characterized in the Time domain.

Could you please tell me what are the reasons for that ?

Thanks in advance.
 

Re: Time domain & Frequency domain Jitter characterizati

In the first case, the PLL is used as a LO, where spectral purity is the ultimate specification. Higher phase noise would introduce reciprocal mixing.
In the second case, it is used as a clock for sampling, where the way the phase noise is spread-out does not matter as long as the area of phase noise curve over frequency axis is kept low (which is jitter).
"Mixing" and "Sampling" clearly differentiate the domain we have to be interested in.
 

    AdvaRes

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top