DC synthesis of sync D-flip-flop maps to unnexpected flop...

Re: DC synthesis of sync D-flip-flop maps to unnexpected flo

The problem I'm having is reproducible w/ the class.db technology library distributed along w/ synopsys design compiler.

I have a very simple synchronous, active-high reset D-flipflop, which I expect to have it mapped
to the tech-mapped flop FD2S (class.db). However, DC synthesize it to the D-flipflop D1
w/ some extra logic fanning-in the 'reset' input pin CD. The mapping is correct, but I was hoping
it would not have the extra logic. I have tried different tricks w/ DC to make the mapping what I
expect, but I have not been successful.

Is there anybody out there who would know to tell DC to use the 'right' flop, tying its 'clear' input pin to the top-level reset pin?

Here's the information for reproducibility

Verilog source code

module a( b, c, d, e);
input b, c;
input [10] d, e;
reg [10] e;
//synopsys sync_set_reset c
always@(posedge b)
if (c)
e <= 2'd0;
else
begin
e <= d;
end
endmodule

Here's my synthesis script syn.tcl (remember to set link and target library to class.db prior to sourcing this script)
analyze -library work -format verilog test2.v
elaborate -library work a
compile
write -format verilog -output a_mapped.v

Here's the a_mapped.v
module a ( b, c, d, e );
input [10] d;
output [10] e;
input b, c;
wire n3, n6, n7, n8;

FD1 \e_reg[1] ( .D(n6), .CP(b), .Q(e[1]) ); // <<<<<<<<---- Not resettable flop
FD1 \e_reg[0] ( .D(n3), .CP(b), .Q(e[0]) ); // <<<<<<<<---- Not resettable flop
NR2 U7 ( .A(n7), .B(c), .Z(n6) );
IV U8 ( .A(d[1]), .Z(n7) );
NR2 U9 ( .A(n8), .B(c), .Z(n3) );
IV U10 ( .A(d[0]), .Z(n8) );
endmodule

Added after 1 hours 36 minutes:

For those of you who have acess to Synopsys documentation:

The answer lies in the following doc:
Design Compiler Optimization Reference Manual, version C-2009.06, Chapter 8 "Sequential Mapping".

Re: DC synthesis of sync D-flip-flop maps to unnexpected flo

See comment in-line with the code :


always@(posedge b)
if (c)
e <= 2'd0; // Why did you use 2'b0? width of e is 10 bits, is it not?
else
begin
e <= d;
end

Re: DC synthesis of sync D-flip-flop maps to unnexpected flo

Sorry, my mistake while copying and pasting the code. Not sure if it had to do w/ the emoticons or something...

Anyway, the definition of 'd' and 'e' should be read as in :

input [1 : 0] d, e;
reg [1 : 0] e;

It turns out DC budgets the synthesis in a way that it will always add extra logic in front of the D-Flip-Flop Data pin unless you specify exactly what flop you want to use.

Fortunately, all these details are well documented in:
Design Compiler Optimization Reference Manual, version C-2009.06, Chapter 8 "Sequential Mapping".