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Help me design a 1001/1111 sequence detector

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radjanohoun

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Hi, I need to design a 1001/1111 sequence detector which produces a 1 output if the current input and the previous three inputs correspond to either the sequence 1001 or 1111. The output 1 is to occur at the time of the forth input of the recognized sequence.
 

verilog codes for sequence detecter

Use the state machine approach. When the first bit (MSB here) occurs, move to the next state. If the second bit matches, move to the third state and so on till the required sequence is achieved. If, the sequence breaks in any intermediate state go back to initial state. If the sequence matches, in the last state (match state) assert the output. Output is de-asserted otherwise.
 

verilog coding for sequence detection

hi radjanohoun,

Wht exactly are u expecting?? the solution or the approach?
As far as the approach is concerned as suggested by thiagu.. use State Machines...

haneet
 

verilog code for sequence detector

Hi Haneet,
Do you need the solution...?
If so what do you want...? Just the state diagram, the digital circuit or the verilog code for it...?
If you want to learn to design it by yourself then you have to learn state machines from a good Digital Electronics Book.
 

state diagrams for sequence detector

Hey Satish..
itz not me whoz asking Qeries abt state machines... i suggesting abt state machines....

haneet
 

vhdl code for sequence detector

Ho Sorry...
It should probably addressed as radjanohoun.
 

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