jadedfox
Member level 1
How do "bufif0" and "bufif1" in Verilog HDL create warning in synthesis?
how does in Verilog HDL "bufif0" "bufif1" creates warning in synthesis?
when can/should they be used to avoid warning?
how does in Verilog HDL "bufif0" "bufif1" creates warning in synthesis?
when can/should they be used to avoid warning?