gaom9
Full Member level 4
non-unate path
Hi,
I am working with a SOC job, but I met some question about the the sequence of Boundary Scan insert and the DFT scan insert, the tools for them are BSD compiler and DFT compiler. Can any one give me some idea, please?
I have tried the two flow:
1 Insert the BSD to the RTL code by BSD compiler and then Synthesis by compile command finnaly insert the DFT by DFT compiler. The BSD insert is successful, but there are some errors as follow:
set_dft_configuration -fix_bidirectional disable -scan enable -fix_clock enable -fix_set enable -fix_reset enable
Error: Boundary Scan Synthesis is mutually exclusive with options :
-scan | -fix_set | -fix_reset | -fix_bus | -fix_bidirectional | -fix_clock | -fix_xpropagation |
-control_points | -observe_points | -wrapper | -scan_compression . (UIT-1313)
Discarded dft configuration specification.
0
insert_dft
Error: Boundary-Scan has already been inserted using 'insert_dft' command. (TEST-2003)
Information: DFT insertion was not successful. There were unrecoverable processing errors. (TEST-211)
0
The DFT insert failed. And I tried to use the set_scan_configuration -exclude_elements command to exclude the BSD cell from DFT, but it failed again.
2 Synthesis the aboriginal RTL code then insert DFT, and finnaly insert BSD to the gate-level netlist after DFT compiler. The DFT insert is successful. But there are some errors as follow
dft_drc -coverage_estimate (after BSD insert)
In mode: Internal_scan...
Design has scan chains in this mode
Design is scan routed
Post-DFT DRC enabled
Information: Starting test design rule checking. (TEST-222)
Warning: Cell top_u/pord_u/alog_u/rom has no function specification.
Warning: Cell top_u/pord_u/log1_u/rom has no function specification.
Loading test protocol
...basic checks...
...basic sequential cell checks...
...checking vector rules...
Error: Line 598 (/tmp/__dft_drc.spf.top.gaom9.18236), invalid state (Clock "trst_n" has value N different from offstate 1 at beginning of Shift procedure). (V13-1)
Error: Line 598 (/tmp/__dft_drc.spf.top.gaom9.18236), invalid state (Clock "tck" has value N different from offstate 0 at beginning of Shift procedure). (V13-2)
Error: Line 599 (/tmp/__dft_drc.spf.top.gaom9.18236), invalid state (Clock "trst_n" has value N different from offstate 1 at end of load_unload procedure). (V13-3)
Error: Line 599 (/tmp/__dft_drc.spf.top.gaom9.18236), invalid state (Clock "tck" has value N different from offstate 0 at end of load_unload procedure). (V13-4)
Error: Could not perform design rule checking. (TEST-1311)
0
and I remove_test_protocol and create_test_protocol again, but
dft_drc -coverage_estimate
In mode: all_dft...
Pre-DFT DRC enabled
Warning: A non-unate path in clock network for clock 'tck'
from pin 'top_DW_tap_inst/u_cell_479/Y' is detected. (TIM-052)
Information: Starting test design rule checking. (TEST-222)
Warning: Cell top_u/pord_u/alog_u/rom has no function specification.
Warning: Cell top_u/pord_u/log1_u/rom has no function specification.
Loading test protocol
...basic checks...
...basic sequential cell checks...
...checking for scan equivalents...
...checking vector rules...
Error: Line 652 (/tmp/__dft_drc.spf.top.gaom9.18236), missing definition (Waveformchar "P" must be defined for "trst_n"). (V4-1)
Error: Line 652 (/tmp/__dft_drc.spf.top.gaom9.18236), missing definition (Waveformchar "P" must be defined for "tck"). (V4-2)
Error: Could not perform design rule checking. (TEST-1311)
0
***************************************************
IEEE 1149.1 Violation Summary
***************************************************
check_bsd successful.
Someone told I should use the first flow, but how to make the DFT compiler do not insert_dft to the BSD cell? I know the BSD cell can generate the patterns itself, and it dose not need the DFT compiler to do that. And what's more, if the design contain the BSD cell, how to generate the patterns in TeraMAX ( BSD cell can generate the patterns itself), is it any difference from the commonly method without it?
Thank you!
Best regards!
Hi,
I am working with a SOC job, but I met some question about the the sequence of Boundary Scan insert and the DFT scan insert, the tools for them are BSD compiler and DFT compiler. Can any one give me some idea, please?
I have tried the two flow:
1 Insert the BSD to the RTL code by BSD compiler and then Synthesis by compile command finnaly insert the DFT by DFT compiler. The BSD insert is successful, but there are some errors as follow:
set_dft_configuration -fix_bidirectional disable -scan enable -fix_clock enable -fix_set enable -fix_reset enable
Error: Boundary Scan Synthesis is mutually exclusive with options :
-scan | -fix_set | -fix_reset | -fix_bus | -fix_bidirectional | -fix_clock | -fix_xpropagation |
-control_points | -observe_points | -wrapper | -scan_compression . (UIT-1313)
Discarded dft configuration specification.
0
insert_dft
Error: Boundary-Scan has already been inserted using 'insert_dft' command. (TEST-2003)
Information: DFT insertion was not successful. There were unrecoverable processing errors. (TEST-211)
0
The DFT insert failed. And I tried to use the set_scan_configuration -exclude_elements command to exclude the BSD cell from DFT, but it failed again.
2 Synthesis the aboriginal RTL code then insert DFT, and finnaly insert BSD to the gate-level netlist after DFT compiler. The DFT insert is successful. But there are some errors as follow
dft_drc -coverage_estimate (after BSD insert)
In mode: Internal_scan...
Design has scan chains in this mode
Design is scan routed
Post-DFT DRC enabled
Information: Starting test design rule checking. (TEST-222)
Warning: Cell top_u/pord_u/alog_u/rom has no function specification.
Warning: Cell top_u/pord_u/log1_u/rom has no function specification.
Loading test protocol
...basic checks...
...basic sequential cell checks...
...checking vector rules...
Error: Line 598 (/tmp/__dft_drc.spf.top.gaom9.18236), invalid state (Clock "trst_n" has value N different from offstate 1 at beginning of Shift procedure). (V13-1)
Error: Line 598 (/tmp/__dft_drc.spf.top.gaom9.18236), invalid state (Clock "tck" has value N different from offstate 0 at beginning of Shift procedure). (V13-2)
Error: Line 599 (/tmp/__dft_drc.spf.top.gaom9.18236), invalid state (Clock "trst_n" has value N different from offstate 1 at end of load_unload procedure). (V13-3)
Error: Line 599 (/tmp/__dft_drc.spf.top.gaom9.18236), invalid state (Clock "tck" has value N different from offstate 0 at end of load_unload procedure). (V13-4)
Error: Could not perform design rule checking. (TEST-1311)
0
and I remove_test_protocol and create_test_protocol again, but
dft_drc -coverage_estimate
In mode: all_dft...
Pre-DFT DRC enabled
Warning: A non-unate path in clock network for clock 'tck'
from pin 'top_DW_tap_inst/u_cell_479/Y' is detected. (TIM-052)
Information: Starting test design rule checking. (TEST-222)
Warning: Cell top_u/pord_u/alog_u/rom has no function specification.
Warning: Cell top_u/pord_u/log1_u/rom has no function specification.
Loading test protocol
...basic checks...
...basic sequential cell checks...
...checking for scan equivalents...
...checking vector rules...
Error: Line 652 (/tmp/__dft_drc.spf.top.gaom9.18236), missing definition (Waveformchar "P" must be defined for "trst_n"). (V4-1)
Error: Line 652 (/tmp/__dft_drc.spf.top.gaom9.18236), missing definition (Waveformchar "P" must be defined for "tck"). (V4-2)
Error: Could not perform design rule checking. (TEST-1311)
0
***************************************************
IEEE 1149.1 Violation Summary
***************************************************
check_bsd successful.
Someone told I should use the first flow, but how to make the DFT compiler do not insert_dft to the BSD cell? I know the BSD cell can generate the patterns itself, and it dose not need the DFT compiler to do that. And what's more, if the design contain the BSD cell, how to generate the patterns in TeraMAX ( BSD cell can generate the patterns itself), is it any difference from the commonly method without it?
Thank you!
Best regards!