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How a self-biasing circuit (latch) is done ?

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As in most of the other designs of the latches, there is always a biasing transistor
connected to the source of the NMOS in the regenerative loop. In that architecture, the biasing transistor is eliminated and self biasing techniques are used to attain required voltage levels and therefore rail to rail output is closely achieved. How a self-biasing circuit is actually accomplished?
Thx in advanced
 

self bias circuit

Hi,

it wil be much easier, if u can post the schematic of the ckt which u refer 2


thanks,
 

self biasing

Blackuni said:
Hi,

it wil be much easier, if u can post the schematic of the ckt which u refer 2


thanks,
Click to expand...

see the file in attachment. It's a latch
 

self biased transistor

Hi,

In reference to u r ckt,

M12 and m13 act as pre charge devices which pull either of out- or out+ to vdd (its explained how this happens in CS amp with diode/active load in razavi)

If you use a resistor to do this job, there will b a drop across it so u r output can't reach vdd any time. which is not the case when u use a pmos device.

the same principle applies to bottom nmos device(but it will be close to zero)

so in total u will get rail to rail swing.

Hope this helps.

Let me know for any clarification.

thanks,
 

    K

    kickbeer

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self biasing circuit

thx very much for that answers. it's really helpful. But i'm still not clear of the function of transistor M5 and M6. Do they amplify the signal in_com+ and in_com-? These two signals are output of the differential amplifier (not seen and the attachment).
 

low voltage self-biasing reference circuits

There are three state for the circuit:
1,0, and bi-stable state
when the clk is high, the self biasing circuit(regenerative circuit) strives out of the former 1 or 0 state, Vout+ and Vout- settle down to the same voltage( at least very closely voltage level).
when the clk is low, the branch of vin- or vin+ ( which one is low enough)will sink a current from the self biasing circuit, the vout+ or vout- node is pulled down, the self biasing circuit will funciton as a positive feedback circuit, make the low one more lower, make the high one more higher.

M5 and M6 are used to read the input signals.
 

    K

    kickbeer

    Points: 2
    Helpful Answer Positive Rating
why use self bias in a circuit

finerain22 said:
There are three state for the circuit:
1,0, and bi-stable state
when the clk is high, the self biasing circuit(regenerative circuit) strives out of the former 1 or 0 state, Vout+ and Vout- settle down to the same voltage( at least very closely voltage level).
when the clk is low, the branch of vin- or vin+ ( which one is low enough)will sink a current from the self biasing circuit, the vout+ or vout- node is pulled down, the self biasing circuit will funciton as a positive feedback circuit, make the low one more lower, make the high one more higher.

M5 and M6 are used to read the input signals.
Click to expand...

I'm not so clear with the sentence 'to read the input signals'. Do they amplify input signals?
 

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