What are TCL and Perl? How are these two languages related to VHDL?

Why do I need TCL and Perl knowledge when I am applying for a job in FPGA designs using VHDL language?

What are TCL and Perl? Why these two languages are related to VHDL?

what is tcl &perl script in asic

Thanks. But I still not very clear what are they for?

perl script for vhdl designer

Since i have migrated recently from Windows environment to UNIX where u use TCL & Perl for scripting is

This is what i found out is

1> TCL: Very closely integrated with ur FPGA Tool. Like u can give ur RTL files to a synthesis tool like Synplify and then use Xilinx par for place and route. This kind of jobs can be easily done using TCL scripts. Also like parameters for synthesis can be specified in some configuration files and u need to read these files and pass the parameters to the synthesis tool like encoding styles, some modes, etc.

2>Perl: Very good scripting language and can be used to parse timing reports, area utilization etc and write this information in a .csv or .xls files.

I am still a newbie in using these languages. But these are some of the things i observed.

vhdl + scripting language

I found TCL a very useful tool for automating simulation in Modelsim and ActiveHDL. It saves a lot of time since when you change source files you only have to run one script file to compile and/or synthesize and simulate a design instead of performing all these operations manually.