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How to describe pipeline circuits to VHDL

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etherios

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adding pipeline vhdl

I am having problem in describing pipeline circuits in VHDL could anyone plz help? I would rather appreciate an example, especially a pipeline adder or better a pipeline carry save array multiplier.
 

The simplest approach is to use the last versions of Synplify, which can automatically introduce pipeline in your design. So, your adder can be described as a process:
Ctmp1<=A+B;
process(clk)
begin
if rising_edge(clk) then
Ctmp2<=Ctmp1;
C<=Ctmp2;
end if;
end process;

If you select Pipeline option in Synplify, the intermediate pipeline register (Ctmp2) will be moved inside the adder design.

Ace-X.
 

Ok i understand. The problem is that when you want to describe an adder you have to add several latches in the input and other in the output which have a relation with the hierarcy of the bits. Example if you want to add 3 bits the you add 1 latche in the input of 0 bit and 3 latches in the output, for bit 1 you put 2 latches in the input and 2 latches in the output and so on. How can i do this?
 

Looks like we are talking about different stuff. You'd better give a look at this paper:
**broken link removed**

It contains well-defined description of pipelining and adder design with VHDL examples.

Ace-X.
 

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