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Verilog State Assignment - equivalent logic in Verilog

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vlsi_freak

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Verilog State Assignment

Hi All,

In VHDL, we can write same set of logic for multiple states as shown below,

when STATE_A | STATE_B =>

----
-----

How we write an equivalent logic in Verilog.

Please help me.

regards,
freak
 

Re: Verilog State Assignment

STATE_A,STATE_B :
 

    V

    vlsi_freak

    Points: 2
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Hi vlsi_freak,

In Verilog for FSM you should use

case()
...
endcase

and you should assign your next state inside case block.

If you explain what do you want to to you'll get better help.

Best Regards,
 

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