Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

any provision of signal attributes in verilog ?

Status
Not open for further replies.
N

nagu guptha

Junior Member level 2
Joined
Dec 5, 2008
Messages
21
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,410
verilog...

Do we have any provision of signal attributes in verilog, like 'event in vhdl.
Is it possible to check positive edge of clock in behavioural statements like TASK and conditional IF statements.
please do reply.....
 

verilog...

'event is similar to @ in Verilog.

@(posedge signal);

Will wait for a postive edge on signal. This can be used in tasks.
 

Re: verilog...

Thank you for replying......,it was a useful information.
 

verilog...

that is right!
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top