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modelsim - "ITERATION LIMIT REACHED" problem

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nagu guptha

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modelsim

In our project while simulating verilog code we are encountering a problem in which it is showing "ITERATION LIMIT REACHED" what is the meaning of it and how to overcome.please someone reply.
 

Re: modelsim

1. check whether the tool is evaluation copy,it has limitations.

2. in your code there might be loop which never ends, this problem mainly occurs .with for loop. check the loops.

i hope it helps , good luck
 

Re: modelsim

Thank u,yours suggestion was very useful for me.
 

I stumbled over the iteration problem with Questasim 6.5. Then I implemented a module to closely study the simulator bahaviour - I still have no clue what the problem could be.

The test module describes two circuits that communicate via two signals, enCalc and calcCpl.
Due to the cross coupling of those signals in the always blocks, delta cycles are executed, but shouldn't the signals be stable after a view cycles?

I also wrote an equivalent VHDL module where this behaviour does not occur.

Can someone please help me out here...

Questa error message
** Error: (vsim-3601) Iteration limit reached at time 16500 ns.

The Verilog code
Code:
`timescale 1 ns / 1 ns

`define MAX_CONTROL_CNT (5)
`define MAX_CALC_CNT (7)

module sandbox();

   time cClockPeriod = 1000;

   reg clk;
   reg nReset;

   reg [2:0] controlCnt, nextControlCnt;
   reg [2:0] calcCnt, nextCalcCnt;
   
   reg enCalc;
   reg calcCpl;

   initial
     begin
	clk = 0;
	nReset = 0;
	forever
	  begin
	     #(cClockPeriod/2) clk = ~clk;
	  end
     end

   always @(posedge clk, negedge nReset)
     begin : seq
	if (~nReset)
	  begin
	     controlCnt <= 0;
	     calcCnt <= 0;
	  end
	else
	  begin
	     controlCnt <= nextControlCnt;
	     calcCnt <= nextCalcCnt;
	  end
     end

   always @*
     begin : controlComb
	nextControlCnt <= controlCnt;
	
	enCalc = 0;
	
	if (controlCnt == `MAX_CONTROL_CNT)
	  begin
	     enCalc = 1;
	     if (calcCpl)
	       begin
		  nextControlCnt <= 0;
	       end
	  end
	else
	  begin
	     nextControlCnt <= controlCnt + 1;
	  end
     end

   always @*
     begin : calcComb
	nextCalcCnt <= calcCnt;

	calcCpl = 0;
	
	if (enCalc)
	  begin
	     nextCalcCnt <= calcCnt + 1;
	     if (calcCnt == `MAX_CALC_CNT)
	       begin
		  calcCpl = 1;
		  nextCalcCnt <= 0;
	       end
	  end
     end // block: calcComb

   initial
     begin : stimulus
	#(5*cClockPeriod+1);
	nReset <= 1;
     end
endmodule // sandbox

The VHDL code
Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity sandbox is

end entity sandbox;

architecture bhv of sandbox is

  constant cClkPeriod : time := 1 us;
  
  constant cMaxControlCnt : positive := 5;
  constant cMaxCalcCnt    : positive := 7;
  
  signal clk    : std_ulogic := '0';
  signal nReset : std_ulogic;

  signal controlCnt, nextControlCnt : unsigned(2 downto 0);
  signal calcCnt, nextCalcCnt       : unsigned(2 downto 0);

  signal enCalc  : std_ulogic;
  signal calcCpl : std_ulogic;

begin  -- architecture bhv

  clk <= not(clk) after (cClkPeriod/2);

  seq : process (clk, nReset) is
  begin
    if (nReset = '0') then
      controlCnt <= to_unsigned(0, controlCnt'length);
      calcCnt    <= to_unsigned(0, calcCnt'length);
    elsif (clk'event and clk = '1') then
      controlCnt <= nextControlCnt;
      calcCnt    <= nextCalcCnt;
    end if;
  end process seq;

  controlComb : process (controlCnt, calcCpl) is
  begin
    nextControlCnt <= controlCnt;

    enCalc <= '0';

    if (controlCnt = cMaxControlCnt) then
      enCalc <= '1';
      if (calcCpl = '1') then
        nextControlCnt <= to_unsigned(0, nextControlCnt'length);
      end if;
    else
      nextControlCnt <= controlCnt + 1;
    end if;
  end process controlComb;

  calcComb : process (calcCnt, enCalc) is
  begin
    nextCalcCnt <= calcCnt;

    calcCpl <= '0';

    if (enCalc = '1') then
      nextCalcCnt <= calcCnt + 1;
      if (calcCnt = cMaxCalcCnt) then
        calcCpl     <= '1';
        nextCalcCnt <= to_unsigned(0, nextCalcCnt'length);
      end if;
    end if;
  end process calcComb;

  stimulus: process is
    begin
      nReset <= '0';
      wait for (5*cClkPeriod + 1 ns);
      nReset <= '1';
      wait;
    end process stimulus;
    
end architecture bhv;
 

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