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Problem with a SAR ADC with 8 bit resolution

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Monady

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ADC

I designed a SAR ADC with 8 bit resolution. But I have a basically problem. I think that with 8 bit resolution, Quantization error(Vq) must be below than 1V/2^8 = 4mv. Thus comparator can have at most 2mV offset.
Assume that in 8th step we want to determine LSB.if Vin=801mV and Vr(connected to comparator )=800.7mV, in this case if comparator has only 400uV, then we will miss one bit resolution.
If comparator have no any offset, Bout=11001101
But if comparator has even 400uV offset, Bout=11001100
Why this result conflict with previous basis (Vq <4mV) and even 400uV caused problem?
Any help would be appreciated!
 

ADC

The 4mV argument comes only when your reference is 800mV. Basically it means for 8 bit with 1V reference,
the rational numbers that you would worry are 796mV 800mV and 804mV. You dont care what what happens between them.


in other words for 800mV reference from 798mv to 802mV (+/-2mV) if you get 11001000 you are fine with it. assuming that step size constant throughout the transfer curve.

For case you have mentioned it is related to the DNL error where you are changing the step size becuase the reference is 0.7mV more than 800mV.
 

    M

    Monady

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ADC

When you design ADC remember to address Offset error,gain error, DNL and INL errors.
 

Re: ADC

thanks for your replies.
Really i mixed up, thus i wrote some relations in the attached pic, please let me know if i made a mistake.
 

ADC

The ADC op will be 11001101.
corresponding quant err = 801m-800.781mv < LSB.

You need not consider the 11001100 case. If you get this output it means ADC is not ideal and there is any error.

I think you have to consider "800.781mV" not "800.7mV"
 

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