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combinatorial loop in VHDL code synthesis (Please Help)

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sudarsv

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combinatorial loop

Hi

I am facing a warning which says "The following signals form a combinatorial loop". I am trying to build a combinational circuit (this is a part of a complete FSM ie a different process and will not have a clock interface). Here I am using a statement like :

Sum:= Sum + Const;

where Sum is a variable. I think the combinatorial loop is due to this assignment can you please suggest any other method where i can implement this logic.

thank you

Added after 19 minutes:

To add to the description above, I am synthesizing the VHLD code in Xilinx but later it will be synthesized using Cadence.
 

the following signal(s) form a combinatorial loop

Code:
Sum:= Sum + Const;
The expression can only be meaningful when embedded in clocked sequential block.
 

xilinx combinatorial loop

Thank you for the response. Yeah the statement is valid only for sequential block, but in my design, I need to build a FSM in which there is a controller and ALU. The above statement is a part of the ALU which is a combinational process (ie no clk in the sensitivity list). This process is triggered as per changes to the inputs made in different states of the Controller.
Can you suggest me some way in which I can have something like an accumulator in the ALU which will add the different values for different states of the controller. The previous value shud be retained.
 

vhdl loop synthesis

Cause a working accumulator involves a clocked register, it must reside in a clocked sequential block. It's possibly a problem of a unsuitable overall design structure.

Remember that HDL means hardware description language. It's different from sequential processing implemented with procedural programming languages. The adequate behavioural description of a register is clocked sequential block.
 

for loop in vhdl

Think about what you are writing:

sum = sum + const;

you have sum on both sides of the equation! This is bound to create a combinatorial loop. Do something like this:

temp = sum + const;
sum = temp;
 

vhdl for loop

temp = sum + const;
sum = temp;
This doesn't change anything. It's fully equivalent to the original expression. The point is to implement a clock, to achieve that sum get's the new value in the next clock cycle. So it's incremented in a defined away, once every clock cycle.
 

combinatorial loop vhdl

oh good catch, my mistake! Then you must use a clocking scheme to store the value!
 

combinatorial loops

hi guys

thank you for the response..... yeah the accumulator required a clocking scheme... . so I used the same statement but triggered the statement only at the rising edge of the input..... something like, if 'a' is my input to the combinational logic

if(a=1 and a'event) then
acc = acc + const;
end if

this was working
 

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