sudarsv
Junior Member level 1
combinatorial loop
Hi
I am facing a warning which says "The following signals form a combinatorial loop". I am trying to build a combinational circuit (this is a part of a complete FSM ie a different process and will not have a clock interface). Here I am using a statement like :
Sum:= Sum + Const;
where Sum is a variable. I think the combinatorial loop is due to this assignment can you please suggest any other method where i can implement this logic.
thank you
Added after 19 minutes:
To add to the description above, I am synthesizing the VHLD code in Xilinx but later it will be synthesized using Cadence.
Hi
I am facing a warning which says "The following signals form a combinatorial loop". I am trying to build a combinational circuit (this is a part of a complete FSM ie a different process and will not have a clock interface). Here I am using a statement like :
Sum:= Sum + Const;
where Sum is a variable. I think the combinatorial loop is due to this assignment can you please suggest any other method where i can implement this logic.
thank you
Added after 19 minutes:
To add to the description above, I am synthesizing the VHLD code in Xilinx but later it will be synthesized using Cadence.