Problem when designing a MAC block

I am trying to implement a MAC block in Verilog on a Xilinx Coolrunner 2 CPLD. I use the 2 switches on the board to toggle between 4 sets of inputs.

module lcd(bcd,leds,ssegsel, EN, clear, clear_value, clk, out,out1,a1);
input [3:0] bcd;
output [1:7] leds ;
output [3:0] ssegsel;
reg [1:7] leds;
wire [3:0] ssegsel;
input a1, EN, clear, clear_value, clk ;
output out,out1;

reg [31:0] out,out1;
wire [15:0] a, b, clear_value;
wire [1:0] a1;

if (a1==2'b00)
begin
out <= out + 16'b0000000000000001*16'b0000000000000001;
assign leds = 7'b1001111;
end

The problem I am having is that I can't seem to add the product back to the out put term. out =a*b is fine, out = a is fine but when I try to enter out = out + a*b, it synthesizes but the simulator shows that the output value cannot be determined. I also tried doing the sum and product in separate terms but that didn't work

Any help would be appreciated

You have not initialized the "out". if this is a behavioral model us initial statement or use a reset signal to initialize the "out". This should solve your problem