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Is data hazard in pipeline occurred or not in this case?

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win3y

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Hi Dears;

Pipeline has 3 stage such as: Memory Read(MemR)(@slot0), ST1(@slot 1), Memory Write (MemW)(@slot2).
At slot2: (MemW) Memory write back to register buffer A. But at the same time, at slot2: (MemR) memory read data from the same register buffer A.
My doubt is that whether data hazard in pipeline occurred or not occurred in the case above ?

Thank you very much.

W3Y.
 

Thats a good question. Register or buffer has been designed in such a way that at the end of a clock cycle you READ the data and at the beginning of a clk cycle you WRITE the data. So there is no hazard.

So in brief, if you write at the positive edge of the clock and read at the negative edge of the clock, you wont have data hazard problem.

I hope it helps.
 

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    win3y

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tariq786 said:
Thats a good question. Register or buffer has been designed in such a way that at the end of a clock cycle you READ the data and at the beginning of a clk cycle you WRITE the data. So there is no hazard.

So in brief, if you write at the positive edge of the clock and read at the negative edge of the clock, you wont have data hazard problem.

I hope it helps.
Click to expand...

Thank you very much for your idea.
It is data hazard if reading from and writing data to the same register at the same time (same edge of clock), isn't it?
One vote "helped" for you.

W3Y
 

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