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VERILOG: How can I assign unpacked arrays?

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Cluny

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verilog array assignment

Hello,

I have a small problem with Verilog. When I want to assign a unpacked wire array to a input array of an instance it does not work. It seems to me that I can't do it in this way?!?.

For example:
---------------
// I want to connect 1byte-width wires to a component that has also pins which are organized in a array ([7:0] pin [2:0]).


Code: 
wire [7:0] input [2:0];

component instance (.pin(input))  // does not work

component instance (.pin[2:0](input[2:0])  // does not work

component instance (.pin[0](input[0]),
                               .pin[1](input[1]),
                               .pin[2](input[2])
                              );                                  // does also not work


Maybe, is there anyone who can help me with this issue?
I hope there is a way to realise it.
 

verilog assign

Hi,

I would do it with assiging the each of the index to a wire of 8-bit width and then passing the combined as o/p "

wire [7:0] input [2:0];
wire [7:0] tmp1,tmp2,tmp3;
wire [23:0] tmp;

assign tmp1 = input[0];
assign tmp2 = input[1];
assign tmp3 = input[2];

assign tmp = {tmp3,tmp2,tmp1}

and during instantiation you can split tmp or pass it as it is and split the bus inside the sub modeul. may be u might have got what i am trying to say. this is just one of the possibility.

Regards,
dcreddy
 

verilog assign array

Thank you very much. I think that this is very helpful for me.

Cluny
 

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