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serial-to-parallel shift register

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kingmaker

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Im asked to use mentor graphic to design serial-to-parallel shift register. Anyone got idea for this design?
 

Try posting your own ideas first and we can guide you along. This way we wont have to spoon feed you.

**broken link removed**
 

that doesn't sound too hard. you can simply code it up using verilog

always @ (posedge iclk)
begin
q[5] <= q[4];
q[4] <= q[3];
q[3] <= q[2];
q[2] <= q[1];
q[1] <= q[0];
q[0] <= id;
if (cnt == 'h5) cnt <= 'h0; else cnt <= cnt + 1;
end

always @ (posedge iclk)
begin
if (cnt == 'h5) odata <= q[5:0];
else odata <= odata;
end
 

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