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2 Dimensional array accessing in VHDL

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Bhargava Ram

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vhdl port array

What are the different synthesisable ways of accessing a 2D array?
I want to implementa dual port ram of, 16 bit input data and 2bit, 4bit, 8bit data as output.
I know it could be done by using a case statement, but is there any other way? I want to minimise the amount of LE's consumed so if there is any logic that would be a great help.
Also if there is any other book than "****perry, ashenden and bhasker and douglous smith****", that teaches the techniques of logic development in VHDL it please suggest ...
I need it badly they need it early would some one help me out
Click to expand...
 

vhdl array of array

You can declare an array of std_logic_vectors and then access each std_logic_vector with its index.

There is an example: **broken link removed**, "inferring block rams".
 

vhdl 2d array

that link is out of service mate, are there any text books that can be help other than,:!::!::?:

Perry,
Ashenden,
Bhaskar,
Douglous Smith.
 

two dimensional array vhdl

This is a dual-port RAM with data width 16 and 6-bit address. Synthesizable with XST and Synplify as block RAM.

You can find similar examples in XST and Synplify user manuals.

Code: 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity mem1 is
port ( CLK : in std_logic;
WE : in std_logic;
WADDR : in std_logic_vector(5 downto 0);
RE: in std_logic;
RADDR : in std_logic_vector(5 downto 0);
DIN : in std_logic_vector(15 downto 0);
DOUT : out std_logic_vector(15 downto 0) );
end mem1;

architecture behavioral of mem1 is

type ram_type is array (63 downto 0) of std_logic_vector (15 downto 0);
signal RAM : ram_type;
signal read_addr : std_logic_vector(5 downto 0);

attribute syn_ramstyle : string;
attribute syn_ramstyle of RAM : signal is "block_ram";

begin

process (CLK)
begin
if rising_edge(CLK) then
if WE='1' then
RAM(conv_integer(WADDR))<=DIN;
end if;
end if;
end process;

process (CLK)
begin
if rising_edge(CLK) then
if RE='1' then
read_addr<=RADDR;
end if;
end if;
end process;

DOUT<=RAM(conv_integer(read_addr));

end behavioral;
 

sram model vhdl array

Does any one know what are the books to be reffered to master the logics development with minimum logic and signals, any book that is perfect for it
 

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