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Basicaly, the compensation of a three stage operational amplifier is similar to the compensation of two stage amplifier. Three stage amplifier means that there are three points of high impedance in the amplifying chain that will add phase lag that may make the amplifier unstable when the feedback loop is closed.
You must increase the cutoff frequency of two of the high impedance points by lowering the resistance or capacitance at these points (using resistive loading, cascode stages, emitter followers etc.) and lower the cutoff frequency of the third high impedance point so it will be the dominant pole of the entire amplifier chain. You must get maximum 140 degrees phase at the frequency of unity gain of the open loop amplifier to get 40 degree phase margin.
If you want to use the closed loop amplifier in a higher gain than unity gain then compensate the amplifier to the same 40 degrees phase margin at the wanted gain, which means a higher frequency dominant pole and higher open loop gain at lower frequencies (lower closed loop distortion)
Thanks for your reply. I found a three-stage amplifier with a compensation capacitor (and resistor) between the input and output of the last stage, and a compensation capacitor (and resistor) between the input of the second stage and the output of the last. But I don't know the parameters of these compensation devices. The second stage and the last stage form a two-stage amplifier. If I compensate this two-stage amplifier to meet the phase-margin requirements. Then add the first-stage, is it needed to re-tune the parameters of the last-two stage's compensation devices?
The only important issue is the open loop phase margin.
If the compensation of the two last stages gave you an equivalent block with a very high -3dB cutoff frequency then you can compensate the first stage that you add to have a low -3dB cutoff frequency for it to be the dominant pole, and to cause that the total open loop frequency response gain to be unity before you get close to 180 degrees phase, getting a reasonable phase margin.
Why not use PZ analysis to help you? Just move the PZ to where you need.
They are almost independent of each other. ( i acknowledge that the miller cap also add up loading to next stage, but it should be ignorable due to the high gain and thereby the low cap value.)
Why not use PZ analysis to help you? Just move the PZ to where you need.
They are almost independent of each other. ( i acknowledge that the miller cap also add up loading to next stage, but it should be ignorable due to the high gain and thereby the low cap value.)
Thank you very much. I ever tried using PZ to analysis the whole circuits, but failed for nonconvergence. I will try to analysis them as two subcircuits.
Still, I have a question about PZ analysis. According to hspice manual, there are several pole/zero control option, including CSCAL, FSCAL and GSCAL. The defaults are CSCAL=1e+12, FSCAL=1e-9, and GSCAL=1e+3. But in the circuit, capacitance parameters are set in Farad, frequency in Hz, and resistors in Ohm. Is it necessary to change the options?
Thank you again. And thanks to strabush and nathan.
Look for the nested Miller compensation as was mwntioned above. Usually that's how this thing is compensated. You may think of it in the following way. Uncompensated, the amplifier would have 3 poles at least. If you introduce an equivelent Miller cap at the output of the first stage and a zero where the second dominant pole begins you'll cancel it. Then the zero from the second compensation circuit may cancel also the third pole.
To make a nested Miller compensation of a 3-stage amplifier, first compensate the two last stages as if it was a clasical 2-stage amplifier using Miller compensation. Then the two last stages behave as a single pole system.
Now, add the first stage and apply Miller compensation to the first stage and the "composite" output stage (two stages already compensated).
Take care on your zeros (it is not good to have several zeros). If you use resistors to build them, any unaccuracy on your R will move your zero. Think about worst cases in your simulations.
wow - u get a lot of response for this one! here's my addition on how. (Hint: compensate 1st stage)
You already compute gain of three stage as a series multiply... A= A1 * A2 * A3. So no problem there..
And you want GBW of 100MHZ. GBW=A*BW. And since we already know A=A1*A2*A3, we can grab our controlling equation, GBW = A1*A2*A3*BW.
So yes, you can compensate ANY STAGE for the same GBW. You can also do neat convolutions of gain/phase data, and build each stage's comp cap out of one master equation....
Or you can look at it like this. Consider three gain stages of 10 each. 1mV into the first stage becomes 10mV, and 100mV as it passes thru.
If you want 50mV, you gotta inject 5mV into the second stage, or only 0.5 mV into the first stage - THERE U GO! Compensate the first stage, and the downstream stages will follow, since the first stage has A2*A3 effect on the output.
The best way to utilize this is with the highest gain in the first stage - now it's no contest! 1st stage compensation dominates all the way out. This archetecture is natural for micro to macro.
Stage 1 - hi-gain diff amp. Extract tiny microphone signal, tiny optoisolator signal, tiny Isense signal. Hi gain=very fast. Compensate here for best effect.
Stage 2 - mid gain, mid power - although slower than 1st stage, the compensation added back there multiplies through to ensure stability for free here.
Stage 3 - high power output. Slowest, but any noise injected here by a big load will be rolled off by the 1st stage compensation in unity gain mode.
I also found this kind compensation, the third stage output use a capacitor to the first stage negative input, and the third stage is a pmos series with two series resistors. the common terminal of resistor connect to the first stage.which kind of op amp is used to multi voltage of the positive reference voltage. who can help me about this compensation paper or adives, and how to do AC analysis? thanks!
You can also try feedforward compensation. This adds an additional feedforward stage which adds a zero to cancel out the dominant (or nondominant) pole of each stage. The biggest advantage of it is that it doesnt need any large Miller capacitors for compensation, hence giving
decent bandwidths. the biggest disadvantage is the formation of pole-zero doublets. You can check out this paper: Thandri/Martinez, JSSC Feb. 2003
An yeah, this theory works well in practice - I have working proof : ). But all said and done, I doubt if you can get very good phase margin in three stage amplifiers. But if you do rigorous simulations for all corners and worst case load conditions, a PM of 30 should be adequate.
The best way to utilize this is with the highest gain in the first stage - now it's no contest! 1st stage compensation dominates all the way out. This archetecture is natural for micro to macro.
Stage 1 - hi-gain diff amp. Extract tiny microphone signal, tiny optoisolator signal, tiny Isense signal. Hi gain=very fast. Compensate here for best effect.
Stage 2 - mid gain, mid power - although slower than 1st stage, the compensation added back there multiplies through to ensure stability for free here.
Stage 3 - high power output. Slowest, but any noise injected here by a big load will be rolled off by the 1st stage compensation in unity gain mode.
As I know, in two stage amplifier the first stage is normally tuned to medium gain(say 10) for noise and speed concern and the second stage is high gain stage for overall gain.
For the best noise performance, the first stage should have high gain. But then, to maintain linearity, you
might have to share that gain among the stages, so that the 2nd and 3rd stages don't get saturated.
I'm not sure about the "high gain=very fast" part. How can you infer that
a high gain section will also be high speed?
In fact a high gain circuit will have a lower bandwidth and hence, a slower response?
I'm curious, but how far can you push the bandwidth to in a CMOS 3-stage opamp? Surely, there must be a trade off between gain and bandwidth in this kind of architecture.
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