Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

VHDL/module get different simulation result as a component

Status
Not open for further replies.
E

ennian

Newbie level 2
Joined
Nov 14, 2008
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,293
I have a module with one architecture and in the behavioral simulation, I get the result that I want.

But when I use an instance of this module in a new module, the simulation(with the same input values, Ive checked the intern signals) gives a different result (the output is one cycle delayed).

Can anyone help me?
 

Re: VHDL/module get different simulation result as a compone

Your stimulus are not exactly the same. When you simulate the stand alone component your stimulus which are probably synchronous with the clock are applied a little before the active edge of your clock (depending on your testbench setup).
When you simulate the component in a system your "stimulus" to the component are generated by the surrounding logic, and appear right after the active edge. Therefore you see a clock delay in the simulation result. Since you do behavioral simulation you don't see those delays.
 

Re: VHDL/module get different simulation result as a compone

Thank u for your reply. And you're right. And actually even in the behavioral simulation I can see the slight delay in the input for the component.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top