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Proteus and a 27256 EPROM

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wpm

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eprom 27256

I have made a circuit with a 27256 Eprom in Proteus 6.3 & SP1.
Eprom settings: Vpp to +5V, /OE and /CE both to GND, didn't change the Advanced Propeties.
The image file is a BIN file, start address is 0x000 and when I use Debug the memory contents is OK.

The address lines A0..A2 are connected to a counter 74LS90 with a clock of 3.6kHz. The address lines A8..A14 to GND. The address lines A3..A7 connected by a switches so I can put a +5V or GND signal to the input.
The lines A0..A2 are used to move the contents of the Eprom one step further. Using the counter the Eprom output lines D0..D7 don't change by every signal on A0..A2 but stay in one position.
When I disconnect the address lines A0..A2 from the counter and connect them by switches either to +5V or GND the output lines D0..D7 change corresponding to the memory contents.

Why does the circuit don't work with the counter?
 

eprom proteus problem

Hi,

It's better to you send the DSN file.

Bye
 

proteus eprom

Added ZIP file
 

eprom proteus

Because there's a serious bug in the API since they have included the new BUSSES class support, so the address bus will not respond to any digital signal. I have already verified the problem you seen so can confirm the problem does exist with all EPROMs.
It looks like the problem didn't find any solution yet !
 

contents of eprom help proteus

Thanks.

In version 6.2 & SP5 it works fine.
 

Yes, you right. I have investigated a bit more about this particular problem in 6.3 (unfortunately is not the only one). As I said the problem has occurred since they have included the support of API version 1.10 and the IBUSPIN class.

For those having good grasp with Proteus API, I should say that with previous release (i.e. 6.2) when a VSM model had to drive a state on its output, a call to EVENT *IDSIMPIN::setstate (ABSTIME time, RELTIME tg, STATE state) was used. For example to drive a 8-bit bus a contruction like this must be used:

for (i=0; i<8; ++i)
outputs->setstate(time, tg, dout & (1<<i) ? TSTATE : FSTATE);
// dout is the byte to send into the output

Above approach was "time spending" because it required the output was written bit-to-bit (in above example 8 times).

With new IBUSPIN support a bus output may be written "at once" using the member function VOID IBUSPIN::drivebusvalue (ABSTIME time, DWORD value), where the DWORD value is the bus value to be in output.

You can easily understand as this approach adds terrific speed and further efficiency to digital simulation. So, Labcenter has modified most of primitives model to accomodate for above described bus support.

However, this improvement did not achieve success for all primitives and for sure this is the case of digital MEMORY primitive. The 27256 model makes use of MEMORY_15_8 digital primitive and I verified that problem belong effectively to MEMORY primitive. For obscure reasons a digital word written onto the Address bus will not generate any event (or may be they are not simply registered in event structure) so it cannot raise for any output on Data bus.

I'm sure of what I say because I tested a single MEMORY primitive and I used LOGICSTATE Active object as digital address word.
I seen no output events will generated while simulating is on, but stopping simulation and run it again a new Data output will take place with a different Address word.

So, I agree that 6.2 SP5 is stable enough and is worthwhile to use it until all problems will sorted out. I dont uninstalled 6.3 from main partition but I have installed 6.2 SP5 on a different partition and created a further link to it. It looks it works provided that you change destination and working directory using link property and changing Path configuration in Proteus (set Path... option in menu System). The latter is required to address for old models and libraries. Doing so I can have 6.2 and 6.3 available on my desktop and I can switch over one of them just setting Path configuration.

Hope it helps
 

Yup - this is definately a whoopsy in V6.3.
Unrelated to IBUSPIN implementation though - the memory models have been changed to latch the address on change of CE/OE (which is always the case in CPU type applications), but fails if CE/OE constantly active for ROM.

Am told it's fixed in the forthcoming 6.4.
 

I'm told too. :wink:
 

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