Fergu
Newbie level 3
Hi,All,I wrote a testbench , and simulated it in modelsim,but there is an error about textio read, the error information is :
# Fatal error at F:/123/duc_design_restored/duc/test_complex_tb.vhd line 121
--the vhdl code of the section:
data_in
rocess(clk)
file f_bdata : text open read_mode is "test.txt";
variable l_bdata : line;
variable w_bdata : integer;
begin
if rising_edge(clk) then
readline(f_bdata,l_bdata);-- line 121
read(l_bdata,w_bdata);
base_band_data <= CONV_STD_LOGIC_VECTOR(w_bdata,16);
end if;
end process data_in;
is there any error in my vhdl code ,pls help me ,thanks in advance!
best regards
Fergu
# Fatal error at F:/123/duc_design_restored/duc/test_complex_tb.vhd line 121
--the vhdl code of the section:
data_in
rocess(clk)file f_bdata : text open read_mode is "test.txt";
variable l_bdata : line;
variable w_bdata : integer;
begin
if rising_edge(clk) then
readline(f_bdata,l_bdata);-- line 121
read(l_bdata,w_bdata);
base_band_data <= CONV_STD_LOGIC_VECTOR(w_bdata,16);
end if;
end process data_in;
is there any error in my vhdl code ,pls help me ,thanks in advance!
best regards
Fergu
