koggestone
Member level 4
interview questions set up hold time
This thread has answers to the interview questions at following thread
So please read above thread , before u read this thread.
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1) As Temp increases ,
Mobility Decreases ,
hence dynamic current (Ion) decreases
hence digital gates run slower at Higher Temperatures
As Temp Increases ,
Vt (Threshold Voltage) Decreases,
hence Leakage current (Ioff) increases
hence Leakage power increases at Higher Temperatures
As a side note , the equation for Ion is
Ion = a . mobility . (Vgs-Vt)^b
note that as temperature increases,
- mobility decreases , which tries to decrease Ion
- Vt decreases , which tries to increase Ion
but the combined effect will effectively decrease Ion and hence digital gates runs slower at high temperature.
But with new processess like 45nm , where nominal Vdd is becoming Lower , and people are being more aggressive to decrease Vdd further to save power, the effect of Vt is bigger than mobility on Ion , hence at high temperatures , digital gates are running faster! . so have your standard cell libraries characterized for various temperatures and use appropriate corner for your STA runs depending on your targetted Voltage at which the block runs.
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2) True
but with newer process like 45nm , and with lower Vdd than process recommended Nominal Vdd , Low Temperature (0c or -40c) is worst case corner instead of traditional High temperature (110c or 125c) .
refer to the answer for 1) above for more explanation.
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3) True
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4) True
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5) Pros - Faster Gate delays
(since as tox decreases , cox increases , hence Ion increases, hence gate delay decreases)
Cons - Higher Gate Leakage , and Reliability Issues
to combat gate leakage , Intel's Future processes has High-K .
since cox is proportional to K/tox , to increase Cox u can increase K instead
of decreasing tox , hence your gate leakage is decreased.
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6) Tclk > Tclktoq + Tlogic + Tsetup + Tskew + Tjitter
Tclktoq + Tlogic - Tskew > Thold
key things to note from above equations
a) once the silicon comes back , if u have setup time problem , u can
increase the clock period (Tclk) to fix it , whereas if u have hold
time problem , its a more serious problem and u will need a new
metal fix tapeout .
b) PLL jitter (Tjitter ) is not used in holdtime equation , since hold
time violation is based on same clock edge . (whereas setup time
vioation depends on 2 consecutive clock edges)
c) above equaitons have clock skew in pessimistic directions . U can play
around with clock skews to get extra margin by skewing them in
favourable direction to decrease violation .
d)from above equations , u can easily answer questions like
"how do u fix setup violations ?" ( faster flop , flop with less setup time , smaller logic between flops , etc ...)
"how do u fix hold violations ?" ( use mindelay flop i.e flop with bigger clock to q , etc ... )
----------
7) Dynamic Power = alpha * C * V^2 * f
(actually the term V^2 is Vdd * Vswing)
so to decrease Dynamic power
a) decrease alpha (activity factor) - clock gating , data gating , reducing toggling of various nodes especially high capacitance nodes , etc ...
b) decrease C (Capacitance) - move to newer process (like 45nm) , smaller gates , smaller wires , ...
c) decrease V - note that power depends on square of V . Hence u get bigger bang for a buck by decreasing Vdd . hence operate blocks that have enough timing margin with lower supply voltages (voltage islands , ...) , low swing Logic ,etc ...
d) decrease f - operate blocks that have enough timing margin with lower clock frequencies (Multiple clock domains, ...) , etc ...
e) u can use Dynamic Voltage Frequency Scaling (DVFS) , by playing around with voltage and Frequency together .
---------
8 ) gate delay t = C . deltaV / I
( deltaV is the Voltage swing)
to decrease gate delay (t)
a) decrease C - reduce output loading (fanout) , newer process like 45nm , etc ...
b) decrease deltaV - reduce voltage swing , etc ...
c) Increase I - bigger transistors (bigger W) , smaller L , etc ...
note that reducing Vdd than process nominal Vdd increases gate delay bcoz
- deltaV decreases proportional to Vdd , hence tries to decrease t
- I decreases proportional to (Vdd-Vt)^a , where a is between 1and 2 , hence tries to increase t
the combined effect will increase t , i.e higher gate delay.
-----------------------------------------------------------
This thread has answers to the interview questions at following thread
So please read above thread , before u read this thread.
-------------------------------------------------------------
1) As Temp increases ,
Mobility Decreases ,
hence dynamic current (Ion) decreases
hence digital gates run slower at Higher Temperatures
As Temp Increases ,
Vt (Threshold Voltage) Decreases,
hence Leakage current (Ioff) increases
hence Leakage power increases at Higher Temperatures
As a side note , the equation for Ion is
Ion = a . mobility . (Vgs-Vt)^b
note that as temperature increases,
- mobility decreases , which tries to decrease Ion
- Vt decreases , which tries to increase Ion
but the combined effect will effectively decrease Ion and hence digital gates runs slower at high temperature.
But with new processess like 45nm , where nominal Vdd is becoming Lower , and people are being more aggressive to decrease Vdd further to save power, the effect of Vt is bigger than mobility on Ion , hence at high temperatures , digital gates are running faster! . so have your standard cell libraries characterized for various temperatures and use appropriate corner for your STA runs depending on your targetted Voltage at which the block runs.
-----------
2) True
but with newer process like 45nm , and with lower Vdd than process recommended Nominal Vdd , Low Temperature (0c or -40c) is worst case corner instead of traditional High temperature (110c or 125c) .
refer to the answer for 1) above for more explanation.
-----------
3) True
----------
4) True
----------
5) Pros - Faster Gate delays
(since as tox decreases , cox increases , hence Ion increases, hence gate delay decreases)
Cons - Higher Gate Leakage , and Reliability Issues
to combat gate leakage , Intel's Future processes has High-K .
since cox is proportional to K/tox , to increase Cox u can increase K instead
of decreasing tox , hence your gate leakage is decreased.
----------
6) Tclk > Tclktoq + Tlogic + Tsetup + Tskew + Tjitter
Tclktoq + Tlogic - Tskew > Thold
key things to note from above equations
a) once the silicon comes back , if u have setup time problem , u can
increase the clock period (Tclk) to fix it , whereas if u have hold
time problem , its a more serious problem and u will need a new
metal fix tapeout .
b) PLL jitter (Tjitter ) is not used in holdtime equation , since hold
time violation is based on same clock edge . (whereas setup time
vioation depends on 2 consecutive clock edges)
c) above equaitons have clock skew in pessimistic directions . U can play
around with clock skews to get extra margin by skewing them in
favourable direction to decrease violation .
d)from above equations , u can easily answer questions like
"how do u fix setup violations ?" ( faster flop , flop with less setup time , smaller logic between flops , etc ...)
"how do u fix hold violations ?" ( use mindelay flop i.e flop with bigger clock to q , etc ... )
----------
7) Dynamic Power = alpha * C * V^2 * f
(actually the term V^2 is Vdd * Vswing)
so to decrease Dynamic power
a) decrease alpha (activity factor) - clock gating , data gating , reducing toggling of various nodes especially high capacitance nodes , etc ...
b) decrease C (Capacitance) - move to newer process (like 45nm) , smaller gates , smaller wires , ...
c) decrease V - note that power depends on square of V . Hence u get bigger bang for a buck by decreasing Vdd . hence operate blocks that have enough timing margin with lower supply voltages (voltage islands , ...) , low swing Logic ,etc ...
d) decrease f - operate blocks that have enough timing margin with lower clock frequencies (Multiple clock domains, ...) , etc ...
e) u can use Dynamic Voltage Frequency Scaling (DVFS) , by playing around with voltage and Frequency together .
---------
8 ) gate delay t = C . deltaV / I
( deltaV is the Voltage swing)
to decrease gate delay (t)
a) decrease C - reduce output loading (fanout) , newer process like 45nm , etc ...
b) decrease deltaV - reduce voltage swing , etc ...
c) Increase I - bigger transistors (bigger W) , smaller L , etc ...
note that reducing Vdd than process nominal Vdd increases gate delay bcoz
- deltaV decreases proportional to Vdd , hence tries to decrease t
- I decreases proportional to (Vdd-Vt)^a , where a is between 1and 2 , hence tries to increase t
the combined effect will increase t , i.e higher gate delay.
-----------------------------------------------------------