What is the difference bettween fault collapsing and fault uncollapsing?

What is the difference bettween fault collapsing and fault uncollapsing? For AND gate, how many faults are required for fault collapsing? let me know

Re: Fault collapsing

Hi Kiranks9,

By fault collapsing we are trying to reduce the number of faults on which ATPG will run. To understand fault collapsing consider a AND gate. In all it will have 6 faults.

Pin A,B and Z stuck-at-0 and stuck-at-1

Now consider the fault Z -stuck-at-0 , A -stuck-at-0, B -stuck-at-0 . The same pattern is used for all these faults.

A = 1
B = 1
Z = 1/0 Fault free 1 and faulty 0

All these faults are equivalent and hence if the tool generate the pattern for a single fault out of these 3.

So, out of 6 it is 4 faults for which ATPG will be done.

-cheers
vlsi_eda_guy

Re: Fault collapsing

HI,

Collapsing typically reduces the total number of faults by 50 to 60%. Fault collapsing for stuck-at faults is based on the fact that a SA0 at the input to an AND (NAND) gate is equivalent to the SA0 (SA1) at the output of the gate. Similarly, a SA1 at the input to an OR (NOR) gate is equivalent to the SA1 (SA0) at the output of the gate. For an inverter, a SA0(SA1) at the input is equivalent to the SA1 (SA0) at the output of the inverter. Furthermore, a stuck-at-fault at the source (output of the driving gate) of a fanout-free net is equivalent to the same stuck-at fault at the destination (gate input being driven). Therefore, the number of collapsed stuck-at faults in any combinational circuit constructed from elementary logic gates (AND, OR, NAND, NOR and inverter) is given by:

Number of collapsed faults = 2 x (number of POs + number of fanout stems) + total number of gate (including inverter) inputs – total number of inverters.

It may help you.

Thanks..

HAK..

Fault collapsing

fault collapsing is of two types fault equilance collapsing generally happens with input faults and fault dominance collapsing for output faults

Hi,according to me...........
for example for an AND gate, we can say 6 faults(SA0/SA1 at A i/p,SA0/SA1 at B i/p,SA0/SA1 at Z o/p)
uncollapsed faults= total no.of faults in the circuit(for an AND gate we can say 6 are uncollapsed faults)
collapsed faults=reducing equivalence and dominance faults
for an AND gate (SAO at any i/p is equivalent to SA0 at the O/P) means-3 faults
and dominance faults(SA1 at o/p is dominated by SA1 at i/p) means-1 fault
so,total collapsed faults are 4(3 equivalence+1 dominance)................
it may help u..................