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Verilog code for frequency divider (50 Mhz to 1 kHz)

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ph333sh

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what would the verilog code be to change a 50MHz clock to 1kHz with a reset input.
 

verilog code frequency divider

module fredivider(clk,rst,clk_out);
input clk,rst;
output clk_out;
reg counter[15];

always @(posedege clk or negedge rst)
begin
if(!rst)
counter<=16'd0;
else
if(counter==16'd5000)
counter<=16'd0;
else
counter<=counter+1;
end

assign out_clk<=counter[15;

end module







I think this code should work...
it might have syntax errors though...
 
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    F.D

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Re: frequency divider

a small modification to lordsatish code :

use assign out_clk = (counter == 16'd5000);

instead of assign out_clk<=counter[15;

and declare counter as reg[15:0] counter;
 

Re: frequency divider

The duty cycle in the previous code would be 50%
and this modification will give you 0.02%...
correct me if i am wrong...!
 

frequency divider

Thats true lordsatish !!!

You would get only 0.02% duty cycle with my assignment statement

But u can get 50% duty cycle with assign out_clk = (counter <= 16'd25000);
 

frequency divider

would

if(counter >= 5000)

work? would that be 1kHz?
 

Re: frequency divider

This is a Divide by 5000 counter...
So there is no point in the count value being greater than 5000...
However there will be clk_out when count value is equal to 5000...
So it will work...
 

Re: frequency divider

I think that correct value 4999!
From 0 to 5000 you have 5001 pulses
 

Re: frequency divider

Hope this modified code will give u a 1khz output clock for an input of 50Mhz clk with 50% duty cycle, correct am if am wrong


module fredivider(clk,rst,clk_out);
input clk,rst;
output reg clk_out;
reg [15:0] counter;

always @(posedege clk or negedge rst)
begin
if(!rst)
begin
counter<=16'd0;
clk_out <= 1'b0;
end
else
if(counter==16'd25000)
begin
counter<=16'd0;
clk_out <= ~clk_out;
end
else
begin
counter<=counter+1;
end
end

endmodule
 
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    9651

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frequency divider

Hello, i'm trying to divide 100 MHz clock by 11 and 22 to get 9.091 MHz and 4.545 MHz clock outputs.
I'm using XC9536XL. I thought of using FDD (Double Edge Triggered Flip Flop), but it's not available to XC9536. How can i do it ? Thank's
 

Re: frequency divider

Hi,

I tried to change this code to get a larger duty cycle.


module coinsorter(clk,rst,top_motor);
input clk,rst;
output reg top_motor;
reg [15:0] counter;
always @(posedge clk or posedge rst)
begin
if(rst)
begin
counter<=16'd0;
top_motor <= 1'b0;
end
else
if(counter==16'd12500)
begin
top_motor <= 1'b1;
counter<=counter+1;
end
else
if(counter==16'd50000)
begin
counter <= 16'd0;
top_motor <= 1'b0;
end
else
begin
counter<=counter+1;
end
end
endmodule


The simulation shows that it's working but when I actually apply it to the RC servo motor it doesn't work.

Also I am trying to control this with an external switch.
I don't want the motor to run unless the switch is on, but it keeps giving me errors whenever I try to compile (The code I posted doesn't include the switch bit, obviously)
 

Maybe because your pwm frequency and/or duty cycle values are wrong?

**broken link removed**
 

Maybe because your pwm frequency and/or duty cycle values are wrong?

l

Using resistors the motor now turns 360 degrees (not just a maximum of 180). I need a frequency of 1KHz to rotate it clockwise and 2KHz for anti-clockwise.
So I think the frequency is right because the motor does rotate with a duty cycle of 50% at 1KHz and 2KHz
Only when I try to change the on time does it not work.
 

Any other handy bits of information? The information in your last post is a bit hard to guess based on your first post. :p That, and we don't even know what clock frequency you use for that coinsorter module...

Also ...

The simulation shows that it's working but when I actually apply it to the RC servo motor it doesn't work.

Kindly post testbench code as well. That always helps.
 

Using resistors the motor now turns 360 degrees (not just a maximum of 180). I need a frequency of 1KHz to rotate it clockwise and 2KHz for anti-clockwise.
Doesn't seem to refer to a standard RC servo.
 

Wasn't going to be the first to bring that up explicitely. Thought I'd just be the first to bring that up implicitly by including **broken link removed**.

Case in point being: 50 Hz PWM frequency, pulse width on the order of 1-2 ms and all that. So that 1 kHz / 2 kHz scheme looked a bit curious....

So a bit more information on the design probably wouldn't hurt.
 

Re: verilog code frequency divider

Hey i cant get 50 per duty cycle.. how would i in this code??
 

Maybe in another 5 years this thread will have accumulated enough 1-poster fragments to start making some sense. :)
 

Dear All,

I am using clock divider where you will see verilog code in followinx text:
But I need to control the frequency using external register.

Could you please let me know how I should do it.
Thank you very much for your help in advance.

module clock_divider(my_clk,clk_div,timer_divider);
input my_clk;
input reg [31:0] timer_divider;

reg [31:0] count; // clock divider counter

output reg clk_div; // clock divider output

always @ (posedge my_clk)
begin

// if(count == 32'b(timer_divider)) // timer_divider should assign to register where I can control it
if(count ==32'b1111101000)
count <= 32'b0000; // reset to 0
else
count <= count+1; // increment counter
clk_div <= (count == 32'b0000);
end
 

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