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FSM rtl coding techniques for a pipelined datapath?

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fsm, pipelining

I am looking for a book or papers that describe systematic rtl coding techniques to design an FSM for a pipelined datapath. I am looking for actual examples that focus on designing and coding of an FSM for a pipelined datapath.

For example:
Techniques to ease coding and minimize the chance of an error.
Techniques and strategies how to deal with pending memory read-writes in case of a pipeline stall, etc.

I am waiting for your suggestions.
Many thanks
Savour
 

Many thanks pmat, but i am looking for coding styles and techniques specially for designing FSMs for a pipelined datapath that also includes memories (SRAMs).
 

pipelined datapath that also includes memories?
 

I mean that the data are fetched from local SRAM memories to the datapath.
 

if sram is synchronous , cen signal which is linked to sram_cen pin must be combined generation using next level stop signal and this level's chip enable signal.
for example:
sram_cen = level1_stop || level0_cen;

maybe this is useful for u.
 

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