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MUX implementation in Verilog case statements/ if else statements

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santumevce1412

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A 4-1 mux written in verilog case statement will be implemented in hardware as .....?
A 4-1 mux written using if else statements in verilog will be implemented in hardware as ...?

My question is both hardware implementation is same or different?

pls explain elaborately......
 

mux implementation

The implementation can be the same or different (depending upon the synth tool).
 
Re: mux implementation

in my opinion, it can be the same or different depend on your writting style.
it have not relation with synthesize tool.
 

Re: mux implementation

It depends upon the exact coding style. I have explained it in detail in one of my MSc reports Please see pages 34,35,36 which explains your doublt very clearly
http://www.vlsiip.com/ipba.pdf
Kr,
Avi
 

Re: mux implementation

avimit said:
It depends upon the exact coding style. I have explained it in detail in one of my MSc reports Please see pages 34,35,36 which explains your doublt very clearly
http://www.vlsiip.com/ipba.pdf
Kr,
Avi
Click to expand...
Hmm, I'm not sure page 35 is such a good example. The two bits of code are not equivalent (e.g. consider when more than 1 myvarN is asserted.) What you want to do is compare an if against a casez. (It's no surprise that functionally different code synthesizes to something else, right?)
 

Re: mux implementation

Hmm, I'm not sure page 35 is such a good example. The two bits of code are not equivalent (e.g. consider when more than 1 myvarN is asserted.) What you want to do is compare an if against a casez. (It's no surprise that functionally different code synthesizes to something else, right?)
Click to expand...

I wanted to exactly highlight the case when only one select line is '1' and rest are '0'. Some ppl would code it using and if-elsif, not konwing that it will result in a priority. That is what I have tried to explain.
I wont use casez or casex as that is not my point.
Kr,
Avi
 

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