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Conditional Instantiation of a Module in Verilog

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omara007

omara007

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verilog module instantiation

Hi folks

How can I make a conditional instantiation of a certain module in Verilog. In other words, if I have a parameter like (number_of_ports) sit to a specific value .. say '32' .. and I want to instantiate a certain module 32 times accordingly .. I need something to check for the value of this variable and generate the required instances accordingly .. and if I change the value of this variable, the number of instantiated modules will change as a result ..

In VHDL, this is simply implemented as (generate) statement .. if gives you the option to instantiate a generic instance inside the generate loop .. and you easily pass the desired number of instances as the loop counter ..

How can this be implemented in Verilog ?
 

verilog instantiation

I suggest to consult the Verilog IEEE specification or a qualified textbook.

The Verilog generate construct can works based on module parameters, they can be modified in instantiation through defparam statements.

Code: 
parameter BURST_MODE = 0;
generate
  if (BURST_MODE==1) begin
  end
  else begin
  end
endgenerate
 

instantiation in verilog

generate construct is not very good to use!
 

verilog instantiate module

ljxpjpjljx said:
generate construct is not very good to use!
Click to expand...

why ? .. i usually use it in VHDL with no problem.
 

verilog ifdef parameter

i usually use it in VHDL with no problem
Click to expand...
Yes, apart from some implementation details, Verilog offers the same functionality in this point, I think.
 

verilog instantiation module

Generate command is fine! You can also use ifdefs, but i also suggest generate as the best solution for your problem!

Pavlos
 

verilog conditional instantiation

may be this example is what you need ?
Code: 
module genvar_example
(
  input   [N*8-1:0]  a, b,
  output  [N*8-1:0]  out
);
parameter N = 4;
genvar i;

  generate for ( i = 0; i <= N-1; i = i+1 )
    begin: inst
      sum sum_i ( .in1(a[8*i+7:i*8]),
                  .in2(b[8*i+7:i*8]),
                  .out(out[8*i+7:i*8]) );
    end
  endgenerate
endmodule

module sum
(
  input  [7:0] in1, in2,
  output [7:0] out
);
assign out = in1 + in2;
endmodule

works with verilog2001;
the code implements 4 times sum module
in the genvar_example top level;


---
 

verilog parameterized module

Hi, On a different note would like to ask which tool did you use to generate the graphic above?
 

verilog module parameter

You get similar graphics with synthesis tools netlist viewer, e. g. from &#65ltera Qu&#97rtus II.
 

verilog parameter module

Note that the Verilog generate statement was added with the Verilog 2001 standard and is not supported by all tools. Generate should not be used if your design must be compiled by any unknown tools.

Without generate the best way to do conditional instantiation of modules in Verilog is with `ifdef PARAMETER and `endif surrounding the module instantiation and `define PARAMETER in a configuration file that is included with `include in the Verilog source file making the instantiation.
 

verilog conditional

for conditional instanciation of module you can use

`ifdef Defination
'else

and in same file you have to include file like
`include "user_defines.v"

and in user_defines.v file you have to define your defination from which you want to instantiale module.

I havent tried this way for perticular thing but it may work here also.

Hth

if you get it working then reply me.
 

conditional instantiation in verilog

EDIT-- nevermind. i should have been using generate to begin with.. ignore the rest of this post.

I'm trying to do something similar, but rather than conditional, it's just repetitive, with different driving and output signals.

the issue i'm having is module naming though..

here's an example using multiple sram modules in system verilog syntax:

Code: 
module sram #(parameter WIDTH=16, DEPTH=1024, A_SIZE=10)
(input clk,
 input [A_SIZE-1:0] rd_addr,
 input [A_SIZE-1:0] wr_addr,
 input [WIDTH-1:0] d_in,
 input we,
 input re,
 output logic [WIDTH-1:0] d_out);

logic [WIDTH-1:0] data [DEPTH-1:0];

always @(posedge clk) begin
   if (we) begin
      data[wr_addr] <= d_in;
   end
   if (re) begin
      d_out <= data[rd_addr];
   end
end
endmodule

then later in some other module...
Code: 
logic [63:0] wr_en_bus;
logic [63:0] rd_en_bus;
logic [15:0] d_in;
logic [15:0] d_out [63:0];
logic [9:0] rd_addr;
logic [9:0] wr_addr;

integer i;
for(i=0; i<64; i=i+1) begin
   sram #(WIDTH=16, DEPTH=1024, A_SIZE=10) //the parameters are unnecessary here, but included for completeness
      ram_number_i (.clk(clk),
       .rd_addr(rd_addr),
       .wr_addr(wr_addr),
       .d_in(d_in),
       .d_out(d_out[i]),
       .we(wr_en_bus[i]),
       .re(rd_en_bus[i]));
end

the main issue is module naming... can modules be named with array notation?
 

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