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Problem with using LUTs in ISE6.1

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alext

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ISE6.1 Bug ??

Hi All!
I got a problem using LUTs (any of them)in
schematic Design in ISE6.1. All signals connected to the Inputs of the LUTs are consedered as unused, so they are removed with LUTs connected to them. The reason of this seem to be wrong *vhf containing additional INIT statement. All this happening when I am using VHDL language in project property, in case of VERILOG all is OK. I'll be vary happy to know that I am wrong! I'll greatly appreciate any help to overcome this very annoing problem. Thanks in advance.
 

Re: ISE6.1 Bug ??

May be you could try to download service pack III. It is available now (31 dec 2003) even if service pack II is supposed to be avaolable next april! ??

Happy new year

Cheers
 

Re: ISE6.1 Bug ??

henrik2000 said:
May be you could try to download service pack III. It is available now (31 dec 2003) even if service pack II is supposed to be avaolable next april! ??

Happy new year

Cheers
Click to expand...

Next Spring (i.e. Spring 2004) = ISE 6.2i, not service pack II. Service pack 3 is the last service pack for ISE 6.1i there will not be anymore.

- Jayson
 

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