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Synchronous and asynchronous

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ushisna

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what is the difference between asynchronous and synchronous SRAM?
 

1. Asynchronous and synchronous refer to whether the SRAM modules have their communications synchronized to match the processor (synchronous = "we're in tune with the processor", asynchronous = "we're not in tune with the processor").
"asynchronous" SRAM can introduce wait states into data transfers.

2. SRAM can be synchronous, or asynchronous. Asynchronous SRAM is not dependent on the clock frequency of the CPU, while synchronous SRAM synchronizes with the CPU clock speed.

3.Synchronous memory design offers several advantages over
asynchronous memory design. Simpler timing requirements allow
synchronous memory to operate at much higher frequencies, resulting in
higher memory bandwidth. Synchronous operation is not prone to errors
because signals are registered on clock edges, simplifying the design
process. A write-enable control circuit is not required because the memory
block controls the write strobe generation, saving on resource usage and
simplifying the design. Additionally, synchronous memory consumes
little standby power.
whereas Asynchronous memory requires that you create a
write enable control circuit to generate a pulse every time a write
operation occurs. You must consider write address setup and hold time
and data setup and hold time on the rising and falling edge of the write
enable pulse. The write enable must toggle on every write operation, as
the address cannot change while the write enable is active.
 

    ushisna

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Synchronous means there is always areference clock so data and addressss are sampled only on the rising and falling edges of the clocks.When we talk about the asynchronous circuit it does sample on rising and falling edge.obviosly asnchronous are faster than synchronous circuit.
 

A write-enable control circuit ? could you please let me understand this point.I could not get this term exactly?can you explain briefly ?:|
 

A programmable circuit is used to modify the write enable signal used by static RAMs in cache-based personal computer systems. More specifically, the programmable circuit is used to delay or not delay the trailing edge of the cache write enable (CWE) signals in cache-based personal computer systems thereby enabling the system to accommodate a plurality of microprocessor devices.

A synchronous SRAM comprising an SRAM core having a memory array of a plurality of bytes, having a plurality of byte write drivers, having sense amplifiers, and having I/O buffers; a plurality of byte write registers respectively connected to the write drivers, the byte write registers selectively activating corresponding byte write drivers to input data into the memory array during a write operation; a plurality of data inputs organized into bytes; a byte write enable input; a plurality of byte write inputs; and byte write enable circuitry connecting the byte write inputs and the byte write enable input to the byte write registers and selectively causing individual bytes of the data inputs to be written into the SRAM core when a predetermined asserted logic level is present on the byte write enable input and also depending on the asserted logic level on the individual byte write inputs.

if you dont understand please do come back. I think the first part is simple and easy to understand.
 

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