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clock synchronization in Wakerely

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ASIC_intl

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Hi

Can anyone please let me know the chapters and locations in Wakerely to read about synchronization using FIFO for data bus (e.g. 8 and 16 bits) during clock domain crossing.
 

look at page 676 in wakerly. it gives info on synchronization
 

I find it in page 731. But there it does not write about synchronization with FIFO but it writes of synchronization with two flop synchronizer. Can u please let me know where it describes synchronization with FIFO? Which chapter?
 

instead of answering ur question directly, let me pose a question in return. Have u come across async. FIFOs with read and write pointers working at different frequencies?

I sincerely suggest you to read the two async. FIFO papers from sunburst design. It will be sufficient to answer your questions on data crossing clock domains. here are the link to two papers.

http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO1.pdf
http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO2.pdf
 

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