Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

VHDL code for Pulse Width Modulation (PWM)

Status
Not open for further replies.

gvsm

Newbie level 4
Joined
Aug 10, 2008
Messages
6
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,317
pwm vhdl

how to implement VHDL code for PWM with frequency 1kHz and duty cycle of 20%
 

vhdl pwm

There are some points, that have to be considered before writing PWM code (respectively trying to copy some existing code):

- the modulation scheme can be natural, regular symmetrical or regular asymmetrical sampling

- PWM modulation input can be either relative (+/- 1 range) or absolute (requested output voltage). In the latter case, a bus voltage measurement has to be processed in the PWM generation. The method is particular useful for a multi-channel (3-phase or more) PWM.

Generally, a ramp generator (mostly triangular), a comparator and optionally a sampler (for regular schemes) forms the PWM generator.
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top