how to improve the following timing?

there is a timing report by synopsys primetime.
*************************************************************
Startpoint: xt_aclk (clock source 'xt_aclk')
Endpoint: ad_a_ad (output port clocked by xt_aclk)
Path Group: xt_aclk
Path Type: max

Point Incr Path
---------------------------------------------------------------
clock xt_aclk (fall edge) 7.50 7.50
xt_aclk (in) 0.00 7.50 f
admx/xt_aclk (ad_mux) 0.00 7.50 f
admx/U1/z (mx21d3) 0.41 7.91 r
admx/ad_a_ad (ad_mux) 0.00 7.91 r
ad_a_ad (out) 0.00 7.91 r
data arrival time 7.91

clock xt_aclk (rise edge) 15.00 15.00
clock network delay (ideal) 0.00 15.00
output external delay -11.00 4.00
data required time 4.00
---------------------------------------------------------------
data required time 4.00
data arrival time -7.91
---------------------------------------------------------------
slack (VIOLATED) -3.91
*************************************************************

Startpoint is rising by xt_clk,however Endpoint is falling edge by xt_aclk .

how to improve it ?

does it has any effect?

clock xt_aclk (rise edge) 15.00
output external delay: -11.00
data required time: 4.00
--------------------------------------------------
Startpoint: clock xt_aclk (fall edge): 7.50
--------------------------------------------------
There is no way to optimize this path to meet timing !

Since even zero path delay, the data can not arrive at 4.0 ns.
--------------------------------------------------

Check the following things:
1) true path ? (fall -> rise, possible ?)
2) output external delay value (really needs 11 ns)
3) single cycle path ?
---------------------------------------------------

If all above are true, then maybe you need to pipeline this part.
==> Insert a rising edge Flip-Flop before the endpoint.
Then the timing path will become:
path #1 falling -> rising
7.5 ns -> data required time=(15ns - library setup time)
Have ~ 1/2 cycle (7.5ns) use.
path #2 rising -> rising
0ns -> data required time=(15ns - 11ns)=4 ns
Have ~ 4ns to use.
----------------------------------------------------
Effect:
1 more cycle latency.

joe2moon said:

clock xt_aclk (rise edge) 15.00
output external delay: -11.00
data required time: 4.00
--------------------------------------------------
Startpoint: clock xt_aclk (fall edge): 7.50
--------------------------------------------------
There is no way to optimize this path to meet timing !

Since even zero path delay, the data can not arrive at 4.0 ns.
--------------------------------------------------

Check the following things:
1) true path ? (fall -> rise, possible ?)
2) output external delay value (really needs 11 ns)
3) single cycle path ?
---------------------------------------------------

If all above are true, then maybe you need to pipeline this part.
==> Insert a rising edge Flip-Flop before the endpoint.
Then the timing path will become:
path #1 falling -> rising
7.5 ns -> data required time=(15ns - library setup time)
Have ~ 1/2 cycle (7.5ns) use.
path #2 rising -> rising
0ns -> data required time=(15ns - 11ns)=4 ns
Have ~ 4ns to use.
----------------------------------------------------
Effect:
1 more cycle latency.

Click to expand...

because there are nedege clk driven circuit in my project.Synopsys primetime will product some above report with report_timing command .One is fall edge,and other is rise edge.i don't know if it meet timing because the value is negative.

or if it is a false path,how should i add the constrain?

You can tell the timing is met or violated just from the report:
slack (VIOLATED) -3.91
==> Timing is "violated" !
-----------------------------------------------------------------------
If the timing is met, then you will see the report like
slack (MET) Positive_Slack_Value
-----------------------------------------------------------------------

False path or true path ?
Only you can understand it. (from the spec/RTL code)
-----------------------------------------------------------------------
Syntax:
set_false_path [-from start_point] [-to end_point]
For more detail, just type
> man set_false_path

joe2moon said:

You can tell the timing is met or violated just from the report:
slack (VIOLATED) -3.91
==> Timing is "violated" !
-----------------------------------------------------------------------
If the timing is met, then you will see the report like
slack (MET) Positive_Slack_Value
-----------------------------------------------------------------------

False path or true path ?
Only you can understand it. (from the spec/RTL code)
-----------------------------------------------------------------------
Syntax:
set_false_path [-from start_point] [-to end_point]
For more detail, just type
> man set_false_path

Click to expand...

yes.it is a false path.

The start point is the clock itself(xt_aclk) so it is a part of CTS and in the logic synthesis this should be put as a false path.

thx

efundas said:

The start point is the clock itself(xt_aclk) so it is a part of CTS and in the logic synthesis this should be put as a false path.

Click to expand...

but ,how do the following path add constrain?
************************************************************
Startpoint: SUBTOP/U_REG/U2/Data_Out_reg
(falling edge-triggered flip-flop clocked by TX_ZT_ECLK)
Endpoint: RTX_ZT_EDOUT
(output port clocked by TX_ZT_ECLK)
Path Group: TX_ZT_ECLK
Path Type: max

Point Incr Path
------------------------------------------------------------------------------
clock TX_ZT_ECLK (fall edge) 640.00 640.00
clock network delay (ideal) 0.00 640.00
SUBTOP/U_REG/U2/Data_Out_reg/CKN (DFFNRX1) 0.00 640.00 f
SUBTOP/U_REG/U2/Data_Out_reg/Q (DFFNRX1) 1.14 641.14 r
SUBTOP/U_REG/U2/Data_Out (EEPROM) 0.00 641.14 r
SUBTOP/U_REG/Eprom_Dout (REGMODULE) 0.00 641.14 r
SUBTOP/EEPROM_DATA_OUT_OUTREG (ZX2701_SUBTOP) 0.00 641.14 r
U199/PAD (WC3B82UA) 2.08 643.22 r
RTX_ZT_EDOUT (inout) 0.00 643.22 r
data arrival time 643.22

clock TX_ZT_ECLK (rise edge) 1280.00 1280.00
clock network delay (ideal) 0.00 1280.00
output external delay -1254.00 26.00
data required time 26.00
------------------------------------------------------------------------------
data required time 26.00
data arrival time -643.22
------------------------------------------------------------------------------
slack (VIOLATED) -617.22
************************************************************

it's a half cycle path.pls refer to your output spec,it seemed unreasonable!

I agree with "efundas" regarding first path.
For second path, output external delay looks too high.

Hi Crisp
u r concentrating on the slack report why not look @ the source code itself may be someone can come up with good ideas.
u can try compile ultra to get best results.
if u have arithmetic operators in ur code use design ware foundation library and compile u get better results.
if u can post ur code over here maybe someone can help.

cheers
srinivas

CRiSP said:

there is a timing report by synopsys primetime.
*************************************************************
Startpoint: xt_aclk (clock source 'xt_aclk')
Endpoint: ad_a_ad (output port clocked by xt_aclk)
Path Group: xt_aclk
Path Type: max

Point Incr Path
---------------------------------------------------------------
clock xt_aclk (fall edge) 7.50 7.50
xt_aclk (in) 0.00 7.50 f
admx/xt_aclk (ad_mux) 0.00 7.50 f
admx/U1/z (mx21d3) 0.41 7.91 r
admx/ad_a_ad (ad_mux) 0.00 7.91 r
ad_a_ad (out) 0.00 7.91 r
data arrival time 7.91

clock xt_aclk (rise edge) 15.00 15.00
clock network delay (ideal) 0.00 15.00
output external delay -11.00 4.00
data required time 4.00
---------------------------------------------------------------
data required time 4.00
data arrival time -7.91
---------------------------------------------------------------
slack (VIOLATED) -3.91
*************************************************************

Click to expand...

Is there a special command to count the number of gates/cells from startpoint and endpoint with report_timing ? Perhaps someone has a better method to share ?