always@smart
Full Member level 4
Hold Time Issue!!??
Hi all,
I understand that Hold time violation happens when the data retain too short after the active edge...
But what about, say the data retain for 2 clock cycle, but it falls on the 2nd active edge, does this still consider hold time violation!!??
If yes, so how could I solve the hold time violation for this data signal which comes from external module(Micro-controller), which is not synchronize with the FPGA design clock, but both having same clock frequency(50Mhz).
Thank you for reply and advice.
Regards,
Hi all,
I understand that Hold time violation happens when the data retain too short after the active edge...
But what about, say the data retain for 2 clock cycle, but it falls on the 2nd active edge, does this still consider hold time violation!!??
If yes, so how could I solve the hold time violation for this data signal which comes from external module(Micro-controller), which is not synchronize with the FPGA design clock, but both having same clock frequency(50Mhz).
Thank you for reply and advice.
Regards,