Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Parallel to Serial 36 bits Shift Register

Status
Not open for further replies.

missbirdie

Member level 1
Joined
May 21, 2008
Messages
35
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Location
Egypt
Activity points
1,544
If i want to make a shift register to convert 36 bits from parallel to serial & I have a clock of 182 MHz what's the value of the load ??? shall it be a clock of duty cycle not 50% ??
 

If 182 MHz is the intended bit clock. Why do you think that it should have a particular duty cycle? You need an additional frame clock to designate the word boundary. If I understood the problem wrong, just tell the bit/word rate you're planning.
 

Because load must be 1 for parallel loading & must be 0 for serial output & the input clock period is 5 ns so i thought to design another clock for the load with period 5*36 = 180 ns with duty cycle 1% just as a trigger to enable parallel load..but the serial output is always zero !!!

what do u mean by additional frame clock ??

Added after 23 minutes:

To be more specific.. here is my design in VHDL
 

I think the definition of load signal is irrelevant as long as the purpose of the serializer in design and the properties of the receiver aren't considered. The sender may start it's data frame at an arbitray clock edge, but the receiver has to know it. The signal, that tells the frame boundary is usually designated a frame clock.

In my view, the load signal isn't a clock but a qualifier, it has to keep setup and hold constraints related to the clock. This is achieved without extra care, when the load signal is originated from the same clock domain. If no other requirements exist, it may be simply generated by a 0 to 35 bit counter.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top