Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to disable timing check in post-simulation

Status
Not open for further replies.

gonewithstone

Newbie level 5
Joined
Jun 16, 2008
Messages
9
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,343
I use VCS to run post-simulation, but I don't know how to disable timing check in the simulation. Anyone can tell me? Thanks
 

add +notimingcheck option
 

Do you means use the command: *.sim +dump -l runsim.log +vcs+lic+wait +notimingcheck to disable timing check when simulation??
 

of course, you can use "vcs -help" to get more information or refer the VCS user guide on SOLD.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top