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May a CPLD have 3 clock input? these clock is not relevant.

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wwwrabbit

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They are independent. if it is possible, how can I simulate them? simulate time only have one scale, that means you can not make clock1, clock2 and clock3 asychronous.

Thanks
 

Re: May a CPLD have 3 clock input? these clock is not releva

What do u mean?

Do u want to connect 3 clocks to a CPLD? If so, yes u can.
How to simulate then? Write a testbench for your module, because I guess those clocks are driving some logic, generate these clocks (in your testbench) and simulate then. Use Models!m for example.

If this is not what u want, clarify your question man... 8)

-maestor
 

Re: May a CPLD have 3 clock input? these clock is not releva

Thank u, sir.
I tried this module, in MaxPlus. there is no compile error. but there are limit of assign clk1, clk2, clk3 pins. some pin can be used as normal input, but can not be used as clock input. improper pin assignment cause fit errors.

module test ( clk1, clk2, clk3, count );
input clk1, clk2, clk3;
output[3:0] count;

reg [3:0] count1;
reg [3:0] count2;
reg [3:0] count3;

always@( posedge clk1 )
count1 = count1 + 1;

always@( posedge clk2 )
count2 = count2 + 1;

always@( posedge clk3 )
count3 = count3 + 1;

assign count = count1 + count2 + count3;

endmodule
 

Re: May a CPLD have 3 clock input? these clock is not releva

if you like to have direct and metalized way i think no, if you like to connect only clock you can put also 4 or five or more clocks in your cpld.
verify to have flip flop to use after.
bye.
g
 

Re: May a CPLD have 3 clock input? these clock is not releva

tlp71,
I am not sure i understand you. would you explain in more detail?
I just want to make sure that in CPLD there are a bunch of flip-flop. there is a globel CLK. is it true that clock of all flip-flop connected to globel CLK. if it is true. then we can not have more than one clock input for a CPLD. I guess it is not ture. in Altera CPLD I can use normal IO pin as a clock input.
:)
 

Re: May a CPLD have 3 clock input? these clock is not releva

yes you are right, the global clock is to have the minimun skew between more flip flops clocked whit the same clock.
If you need not related clock you can use every pin in CPLD.
Some Devices can have more input usable as input for dedicated routing clock lines, depending what do you need.
I hope to explain, i am sorry but my english is bad :)
bye.
G.
 

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