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Internal FIFO in-chip implementation

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mfarajma

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Hi,

I have not worked with xilinx chips before, I was wondering if it is possible to build several "relatively big" fifo's (4Kx8bit) in the chips and how much space would I be occuping for them?

I have looked at severla documents,,, but I am confused about one thing (and I don't have experience with xilinx FPGAs) I noticed in the virtex spec. that they have CLBs and RAM blocks, are these different resources, which one can I use, or should I use,

I'd greatly appreciate any help, tips, and possibly links that with provide me more details,,,

Many thanks,

Mo,
 

Re: Internal FIFO?

The Spartan and Vertex series have BRAM (block ram) which is very fast and usable as single port or true dual port. It is in blocks of 2Kbits on the Spartans I've looked at, maybe bigger on the Vertex. They also have distributed RAM which is in small (64byte or less) blocks distributed all over the chip. The BRAM also has parity if you want it.

Look at https://www.xilinx.com

Git
 

Re: Internal FIFO?

Using 4kbit block RAM (BRAM) in xilinx, you can make a 4kx8 fifo using 8 BRAM in a 1kx1-bit configuration! Using distributed ram does not make any sense here.
 

Re: Internal FIFO?

xilinx virtex-II, Virtex-II Pro and Spartan-III families have relatively bif Block RAMs. Each BRAM can be configured as 2Kx8bit. You can combine two BRAMs and develop a 4Kx8bit FIFO easily.
 

Re: Internal FIFO?

hi

FIFO can be build using block rams and CLBS aslo..using CLB alone the resourse taken will be more...16*1 bit can be stored in 1 lut and so more than 3000 lut would be consumed for 4k*8..and other additional resources for counter and extra logic for a fifo...

each block ram is 4k bit dual port ram..so 512*8 bit can be build uisng 1 block ram and so only 8 block rams would be used...along with some extra logic for counters and others build in LUTS...

in spartan device the maximum width configurable in one block ram is 16..if ur width goes to 7 it would take 2 blockram...whereas in virtex i am not sure but it is defenitely more than 16..increase in the width causes decrease in depth for a block ram.

hope it helps
 

Re: Internal FIFO?

Yes, TurboPC is right.

In Virtex-II for example, a BlockRAM is 512x32 -> 2,048x8 ...so with 2 BRAMs you have your 4Kx8bit FIFO.

In a 2V3000 for exmple you have 96 BRAMs so...you can have 48 4Kx8bit FIFOs or a massive one of ~ 196Kx8bit, if you only need memory use an external memory :)

Hi mfarajma, you mention Virtex, forget about Virtex, they are old :sm11: so start looking to Virtex II o Spartan 2/2E docs.

It's very easy to code a FIFO (either asynch or synch) and most of the synthesizers these days will infer the BRAM for you.

Regards,

-maestor
 

I agree with TurboPC and maestor about using BRAMs for FIFO implementation.

But best and simple solution for FIFO implementation is using Xilinx Coregen FIFOs. It is full configurable in terms of width, depth, flags... and you will save a great amount of design time, and also Xilinx give you a behavioural model.

Regards
 

Re: Internal FIFO?

Thank a lot for your comment guys, I do really appreciate your help. I have recently started working on FPGAs, and have been mainly working on Altera (the only resource I could find around here). Previously, I have done relative big projects but ONLY simulation (using Cadence simulator/Altera Max Plus).
Now we are getting some Xilinx boards that I notice are much more powerful. I'll be looking into them in more details,,,

PS TurboPC: you are right the fact is that I am a bit new in this field and unfortunately here in our university there aren't very few (if any) experts in this feild. So I am starting kind of from scratch.

I hope you wouldn't mind me asking more of these basic newbie's questions.

Many Thanks to all.
 

Re: Internal FIFO?

This forum is here to help!

Here's some vhdl sample code for your fifo. One file 'ram.vhd' will show you how to declare a 'generic' ram without using components that are dedicated to Altera or Xilinx. The other file 'fifo.vhd' is a basic fifo examples.

These files have been synthetized using synplify on Spartan 2,2e,Virtex2, Startix, ... I just don't understand why it uses distributed ram for Spartan3...

Anyways... It is for demonstration purposes...

TurboPC
 

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