Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Problem with one Verilog statement

Status
Not open for further replies.
firefoxPL

firefoxPL

Member level 1
Joined
Mar 18, 2008
Messages
41
Helped
7
Reputation
14
Reaction score
2
Trophy points
1,288
Location
Poznan, POLAND
Activity points
1,521
Hello, I am currently porting demo from Xilinx for XUPV2P board for controling VDEC from Verilog to VHDL and I have problem with understanding one phrase:
Code: 
assign TRS = ((~|YCrCb_rg2[9:2]) & (~|YCrCb_rg3[9:2]) & (&YCrCb_rg4[9:2]));
TRS is a 1-bit signal, I did something like this in VHDL but I am not sure whether it is right:
Code: 
 TRS <= ((((YCrCb_rg2(9) nor YCrCb_rg2(8)) nor (YCrCb_rg2(7) nor YCrCb_rg2(6))) nor ((YCrCb_rg2(5) nor YCrCb_rg2(4)) nor (YCrCb_rg2(3) nor YCrCb_rg2(2))))
        and (((YCrCb_rg3(9) nor YCrCb_rg3(8)) nor (YCrCb_rg3(7) nor YCrCb_rg3(6))) nor ((YCrCb_rg3(5) nor YCrCb_rg3(4)) nor (YCrCb_rg3(3) nor YCrCb_rg3(2)))))
        and (((YCrCb_rg2(9) and YCrCb_rg2(8)) and (YCrCb_rg2(7) and YCrCb_rg2(6))) and ((YCrCb_rg2(5) and YCrCb_rg2(4)) and (YCrCb_rg2(3) and YCrCb_rg2(2))));
In fact it is very probable that this is wrong and thats why the project doesn't work :p
 

To my opinion, the translation of the Verilog reductional operators expression is correct exept for the nor chaining which creates wrong polarity. Furthermore I would expect a logical and && between the three partial expressions, but the difference shouldn't matter in this place.

Code: 
TRS <= not (YCrCb_rg2(9) or YCrCb_rg2(8) or YCrCb_rg2(7) or YCrCb_rg2(6) or YCrCb_rg2(5) or YCrCb_rg2(4) or YCrCb_rg2(3) or YCrCb_rg2(2))
and not(YCrCb_rg3(9) or YCrCb_rg3(8) or YCrCb_rg3(7) or YCrCb_rg3(6) or YCrCb_rg3(5) or YCrCb_rg3(4) or YCrCb_rg3(3) or YCrCb_rg3(2)) 
and (YCrCb_rg2(9) and YCrCb_rg2(8) and YCrCb_rg2(7) and YCrCb_rg2(6) and YCrCb_rg2(5) and YCrCb_rg2(4) and (YCrCb_rg2(3) and YCrCb_rg2(2));
 

    firefoxPL

    firefoxPL

    Points: 2
    Helpful Answer Positive Rating
I don't know VHDL, but there's got to be an easier way to write that expression.
The Verilog statement sets TRS to 1 if the following is true:

YCrCb_rg2[9:2] is 00000000
and
YCrCb_rg3[9:2] is 00000000
and
YCrCb_rg4[9:2] is 11111111
 

    firefoxPL

    firefoxPL

    Points: 2
    Helpful Answer Positive Rating
echo47 said:
I don't know VHDL, but there's got to be an easier way to write that expression.
The Verilog statement sets TRS to 1 if the following is true:

YCrCb_rg2[9:2] is 00000000
and
YCrCb_rg3[9:2] is 00000000
and
YCrCb_rg4[9:2] is 11111111
Click to expand...
that should be really helpful thanks a lot
 

Maybe something like this:
TRS <= '1' when ((YCrCb_rg2(9 downto 2) = "00000000") and
(YCrCb_rg3(9 downto 2) = "00000000") and
(YCrCb_rg4(9 downto 2) = "11111111"))
else '0';
 

lucbra said:
Maybe something like this:
TRS <= '1' when ((YCrCb_rg2(9 downto 2) = "00000000") and
(YCrCb_rg3(9 downto 2) = "00000000") and
(YCrCb_rg4(9 downto 2) = "11111111"))
else '0';
Click to expand...
I was thinking exactly the same thing :)
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top