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rom/ram implementation ..

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prashant_sharma

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hello all,

i would like to know that can we create the rom/ram as an array using the following:

first an array say rom:

type rom is array (0 to 8) of st_logic_vector(7 downto 0);

and the create signals , of this type...and the choose values to be stored in it ...

But my question is.. would it be synthesizable??

thanks

Added after 12 minutes:

that rom is 0 to 4 and 7 down to 0
i don kbow where that smiley came from :p
 

Many synthesis tools will infer ROMs and RAMs from your HDL code, if your target device supports it. You may need to write your HDL code in a certain way to get the desired results. Check your synthesis user manual. For example, the "HDL Coding Techniques" chapter in the Xilinx XST User Guide.

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