Two's complement using minimum hardware

Hi...
Can anyone tell me how to compute the two's complement of n bit number using minimum harware... i.e using minimum number of logic circuits...
Is it possible to do this without using a n bit adder...

By mathematic, since 2's complement calculation is:
1. invert n-bits number
2. inverted n-bits number + 1

How about combination of inverter & 1-b incrementer?

Added after 5 hours 12 minutes:

I just had another idea, not sure is it a good one:
V = n-bit input, W = 2's complement n-bit output, 0 =< m =< n
Wm = Vm XOR I(m-1)
Im = Vm OR I(m-1)


*Below is further explanation, sorry if my expression is not comprehensive enough


Inverter + Incrementor
===============
Assume we use a 1-b incrementor, which output Y = X + 1, where both X & Y are n-bit length, given (0 =< m =< n):
m > 0 : Ym = Xm XOR C(m-1)
Cm = Xm AND C(m-1)
m = 0 : Y0 = X0 XOR 1
C0 = Xm ( = Xm XOR 1)

to simplify this equations, assume C(-1) = 1,
for (0 =< m =< n): Ym = Xm XOR C(m-1)
Cm = Xm AND C(m-1)

Since we need invert the input(V) before increment by 1, the formula become:
for (0 =< m =< n): Wm = V'm XOR C(m-1)
Cm = V'm AND C(m-1)

the resulted logics for n-bit 2's complement : n * (2 NOT, 1 XOR, 1 AND)


simplified logic (using Invert signal, I)
========================
previously, for (0 =< m =< n):
Wm = V'm XOR C(m-1)
Cm = V'm AND C(m-1)
Instead of carry bit, Cm, we introduce another signal, Inverter bit, Im = C'm
Wm = V'm XOR C(M-1)
= V'm XOR I'(m-1)
= Vm XOR I(m-1)
==========
Cm = V'm AND C(m-1)
= V'm AND I'(m-1)
= (Vm OR I(m-1))'
Im = C'm = ((Vm OR I(m-1))')'
= Vm OR I(m-1)
=========

the resulted logics for n-bit 2's complement : n * (1 XOR, 1 OR)

if u do not use serial conersion... then You have to use atleast n bit adder and n xor gates... i could not understand ur logic...

What i mentioned actually same with logics in svicent figure. Sorry for bad explanation

Comparing with the figure:
V <=> A
W <=> B
I = output of OR gate from previous bit

very good logic... i appreciate that.... but i want to minimize some gate in that logic further... we can remove the 1st OR and XOR gate because when we take the 2's complement then LSB always same. so there is no need of 1st xor and. we are transfering the GND to the first or gate and its output is giving to the input of second XOR. so in all condition output of 1st OR will depend on A0. so we can directly connect A0 to the second xor.


amit gangwar