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"non-standard utilization" of APEX NIOS 2 board

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childs

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I am developing a VHDL based Internet Device for ASIC implementation. Lately I tried to test the prototype on FPGA. The FPGA available to me is APEX NIOS 2 board.

Somehow my code was not designed for the features, megafunctions and memories of the board and the FPGA (20K200EFC484-2X), I just utilize the logics on the chip(this is what i meant by "non-standard utilization" in the title, pardon me if the phrase is not suitable :p). I encounter 2 probs:

1. The chip does not have enough logic units, as I implement the memory part as logic instead of utilize the chip's memory.

2. On the NIOS board, I don't understand where the FPGA i/o pin connected to. On my Quartus II, the i/o pins are scattered at a few different i/o banks. And I don't know where these pins connected to on the NIOS board, and how should I connect them on the board.

Prob 1. is somehow temporarily avoided as I limit the prototype memory size, however I think the prob will arise again as I continue the project into phase 2, where I need to add in more functions of the system.

I am still fresh at VHDL design and FPGA. Any helps will be appreciated. Thanks to all :)
 

Re: "non-standard utilization" of APEX NIOS 2 boar

Regarding point 1, this sounds as you defined memory in your logic that can't be inferred as on chip RAM, cause you demanded a feature that isn't available. This may be due to an inappropriate clocking scheme or cause you're reading different memory addresses simultaneously. You should clarify first, if you're intended memory operation is compatible with on-chip memory at all. One option to assure usage of on-chip memory is to instantiate a RAM Megafunction explicitely. Or follow the rules for infering RAM from HDL code in Quartus handbook.

The second point isn't clear to me. You should have a board documentation, that clarifies the pin mapping. Also NIOS example designs should be present. I didn't have any documentation of the said board, that has been discontinued by Altera, but if you miss something, Altera support should be able to help you. Also alteraforum is a place, where some users probably may know the APEX board.

P.S.: If the second question simply means how to assign IO pins to a location, this is usually done in Assignment Editor or the Pin Planner tool with recent Quartus versions. However, you need a board documentation to know the pin mapping of connectors and on-board resources. Normally, the pin mapping could be copied from a reference design, it's in a readable form in *.qsf project files and can be pasted to another *.qsf file (of a closed project).
 

    childs

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