childs
Member level 5
I am developing a VHDL based Internet Device for ASIC implementation. Lately I tried to test the prototype on FPGA. The FPGA available to me is APEX NIOS 2 board.
Somehow my code was not designed for the features, megafunctions and memories of the board and the FPGA (20K200EFC484-2X), I just utilize the logics on the chip(this is what i meant by "non-standard utilization" in the title, pardon me if the phrase is not suitable ). I encounter 2 probs:
1. The chip does not have enough logic units, as I implement the memory part as logic instead of utilize the chip's memory.
2. On the NIOS board, I don't understand where the FPGA i/o pin connected to. On my Quartus II, the i/o pins are scattered at a few different i/o banks. And I don't know where these pins connected to on the NIOS board, and how should I connect them on the board.
Prob 1. is somehow temporarily avoided as I limit the prototype memory size, however I think the prob will arise again as I continue the project into phase 2, where I need to add in more functions of the system.
I am still fresh at VHDL design and FPGA. Any helps will be appreciated. Thanks to all
Somehow my code was not designed for the features, megafunctions and memories of the board and the FPGA (20K200EFC484-2X), I just utilize the logics on the chip(this is what i meant by "non-standard utilization" in the title, pardon me if the phrase is not suitable ). I encounter 2 probs:
1. The chip does not have enough logic units, as I implement the memory part as logic instead of utilize the chip's memory.
2. On the NIOS board, I don't understand where the FPGA i/o pin connected to. On my Quartus II, the i/o pins are scattered at a few different i/o banks. And I don't know where these pins connected to on the NIOS board, and how should I connect them on the board.
Prob 1. is somehow temporarily avoided as I limit the prototype memory size, however I think the prob will arise again as I continue the project into phase 2, where I need to add in more functions of the system.
I am still fresh at VHDL design and FPGA. Any helps will be appreciated. Thanks to all