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insufficient LE units

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childs

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I am currently doing ASIC design for my project, when i tried to prototype the device in FPGA for testing, the device cannot fit in due to LE usage too high.

I tried to put my design into APEX NIOS2 board, which uses APEX 20K200EFC484-2X FPGA. My design consisted own sequential access RAM for the device function purpose.

Any recommandation to solve this prob???
 

I don't know much about your design. But generally any FPGA has a limited space for logic. Fore sure you cannot have a very big design in a little FPGA.
But you can do somethings:
1- try to estimate your logic count and compare it with FPGA capacity. If they are close together you can change architecture or even cut some part to fit it in fpga. otherwise try larger FPGA.
 

20K200 is a smaller FPGA related to todays capacities, but it should be good for a complex design anyway. You can set the project device type to any for trial to check the actual LE need, although the compiler would tell you also in case of a failed fit. Furthemore, the resource usage per entity in compilation report and the resource counts given in the hierarchy view should clarify which design element causes the high resource requirement. Not knowing your design in general or detail, I can't give suggestions where to save resources.
 

thx to both of u, I had just continued & expanded with more details I able to explain (I am kind of fresh in this area, sorry :p) this question at:
 

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